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Interesting (maybe?) question here which I am struggling to answer. Hoping someone can help.

I have a capacitor network; 5 caps in parallel and then two modules of that configuration connected in series. I am measuring the voltage of the bottom 5 caps using an Arduino Nano. The Arduino and cap network are only linked by the cap negative (gnd) connected to the Arduino GND pin. A bit crude but means I can measure negative voltages (i.e. 0V registers as 3V3 on the Nano): Circuit Diagram

I charged the circuit up for just shy of 24hrs to 2V4 from V+ to V-. I checked the voltages across each of the caps and they were reasonably balanced (couple of hundred mV at most). I.e. each cap is sat at 1V2, no current into or out of the system (bar a few uA due to cap internal leakage).

Now, I disconnect the V+ power supply (S1 goes to posn 3) and connect a load (to posn 1 of S2). As expected, the network discharges into the load, favouring discharging the caps with lower value series resistors. I.e. C1 & C6 discharge fastest, C5 & C10 slowest.

At ~75min I set the stack to open circuit.

At ~140min I re-apply the load.

The observation/question. When the caps with fast RC constants (C1 & C6) reach 0V across the cap, they are fully discharged. However, they then get pushed negative. I.e. when measuring across the cap, a negative voltage appears. It goes up to negative a few hundred mV. Why? [Note: I have subtracted 3V3 from the voltage readings to get the correct reference with respect to the stack, not the Arduino].

Results

I've scratched my head over this for a while and cannot understand what is driving the negative voltage across that cap, while the others in parallel remain positive.

I've deliberately been vague on the precise readings because the input impedance of my multimeter, and the Nano suck. (I am in progress making a little voltage follower to solve this issue, and, also use a potentiostat rather than an Arduino!) Apologies on this front.

Interestingly, I have modelled this circuit in Matlab and it predicted this. I was somewhat hoping my model was wrong...maybe not?

Many thanks in advance,

Simon

PS: Massive thanks and credit will be given to anyone able to help if they're happy me crediting them on a research paper. If not, happy to not credit (I know some people don't like to be). PPS: I've not gone into detail about what the circuit represents. Happy to elaborate if people are interested (it's a skew-gaussian distribution BTW).

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It goes up to negative a few hundred mV. Why?

That is why series capacitors have bleed/balance resistors across them. A negative reading is a sign that weaker capacitors (less charge) are being reverse charged by stronger capacitors (more charge). The dielectrics are NOT exact from one capacitor to the next, especially high value supercaps.

Capacitors in parallel do not have this reverse-charge issue, but the leakage values of each capacitor add up. Intentional reverse charging >1 volt is NOT recommended, as it is normally part of 'destructive' testing. This can damage the dielectric beyond repair.

EDIT: The high value resistors are part of the problem. Since you have 2 banks of capacitors of the same capacitance per bank, a single series resistor to limit charge current is fine. Add a 100K resistor across each bank for charge balancing, A 1N4007 diode across each bank (white band to + of capacitors) will prevent a discharge imbalance, by acting as a bypass for the bank that discharges faster, until both banks have drained to zero volts.

The larger value resistor 'protects' capacitors much better than with lower value resistors, assuming both capacitors are of same value. Normally capacitors in parallel attempt to level their charge difference, but series resistors can change this effect. The capacitor with larger value resistor will discharge much slower, thus maintaining a higher voltage (at its own terminals) much longer. The large difference in resistor values negate any chance of charge balancing. The difference in capacitor values exacerbates the problem. Look at your capacitors as trying to be equal, then look at your resistor delta values as an upset to this self-balancing act.

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  • \$\begingroup\$ Many thanks for this. So if I simplified this right down to just C6, R6, C10 & R10 (plus the load) and charge up only C10. When I apply the load, C6 would be pulled negative. What I am struggling to understand (maybe it's too late on a Friday!) is how the positive charge on C10 can drive a negative voltage, through two resistors, onto C6? Hmm, I don't feel like I have explained that well \$\endgroup\$ – GreenaGiant Mar 15 at 18:47
  • \$\begingroup\$ The high value resistors are part of the problem. Since you have 2 banks of capacitors of the same capacitance per bank, a single series resistor to limit charge current is fine. Add a 100K resistor across each bank for charge balancing, A 1N4007 diode across each bank (white band to + of capacitors) will prevent a discharge imbalance, by acting as a bypass for the bank that discharges faster, until both banks have drained to zero volts. \$\endgroup\$ – Sparky256 Mar 15 at 21:59
  • \$\begingroup\$ Thanks for the comments. So this is not a problem I am trying to fix; I should've made that more clear. It's a problem I am trying to understand, i.e. the theory of what is driving this negative voltage. The circuit cannot be modified in any way as I am not trying to make it work and balance. It is part of a research project. \$\endgroup\$ – GreenaGiant Mar 16 at 10:59
  • \$\begingroup\$ I added another paragraph to point out a few things brought up by @TimWescott. We will not give you the equations for this, as to some degree it is RC time constants, and variations with voltage over time. \$\endgroup\$ – Sparky256 Mar 16 at 17:40

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