im just learning SRAM. I wanted to ask, consider the 4x4 memory cell array below
If i wanted to select a word line or row, would the row decoder be a 4x1 multiplexer where each wordline is connected to a Vdd to enable a read or write operation on the cells?
So maybe 2 bits can select any 4 wordlines.
And for the Column decoder, will it be another 4x1 decoder, where the each bit line will be connected to the multiplexer 4x1 and this multiplexer connected to a line which can be either 1 or 0?
Where does the sensing amplifier come into this and are there any other peripherals?