The problem

I need to reliably generate a sequence of events based on a digital input trigger signal. With minimal jitter and a predictable deterministic delay.

  • 2 to 5 events
  • The events will be from 10µs to 10ms apart. Better than 5% timing precision, preferably +-2us.
  • Jitter of <100ns
  • Jitter must be randomly distributed, no deterministic patterns
  • The trigger can be as fast as 50kHz or as slow as 0.1Hz
  • Digital configuration interface (via SPI)

Due to regulatory complexity this design will have to be as analog as possible, with perhaps some fixed (non-programmable) logic.

Possible solution path

The solution path that I currently envision is with purely analog monostable multivibrators driven by DACs that set the oscillator currents and some configuration logic. Being analog, any imperfections will be influenced by gaussian noise, thus solving the random distribution of jitter.

But this clearly presents some difficulties due to the three decades of required timing adjustability. Which led me to this question.

The question

Is it possible to design a crystal (or similarly precise) oscillator that has a deterministic and predictable startup transient?

Clearly a crystal oscillator would considerably simplify timings, as it would make possible replacing the monostables with counters. However a fixed oscillator would make the jitter deterministic, as it will be determined by the beat frequency between the trigger source (a processor) and the oscillator. This will cause problems with the averaging of captured evoked signals.

A crystal oscillator that can be deterministically and repeatably started on demand would greatly simplify the problem.

The basic idea

The first idea that came to mind is something as simple as this circuit:


simulate this circuit – Schematic created using CircuitLab

However, crystal oscillators have rather chaotic and unpredictable startup transients that last a long time (which I would assume is due to slow mechanical effects). So this won't work.

Is there a way to achieve this?

  • 2
    \$\begingroup\$ Is there a reason you can't keep your oscillator running continuously and just disconnect it from whatever other circuits you have until your trigger event happens? \$\endgroup\$ – The Photon Mar 15 '19 at 22:28
  • \$\begingroup\$ Or, if you really only need 5% timing accuracy, use a Schmitt trigger oscillator with 1% components. \$\endgroup\$ – The Photon Mar 15 '19 at 22:30
  • \$\begingroup\$ @ThePhoton as I stated above. That would make the jitter deterministic as it would be generated by the beat of this oscillator and the one in the trigger source. \$\endgroup\$ – Edgar Brown Mar 15 '19 at 22:31
  • \$\begingroup\$ Have you considered MEMs oscillators? \$\endgroup\$ – DKNguyen Mar 15 '19 at 22:35
  • \$\begingroup\$ @ThePhoton i wrote that requirement thinking of what would be possible with such implementation. But I’d really would prefer to achieve ~1us in 10ms, or 100ppm. \$\endgroup\$ – Edgar Brown Mar 15 '19 at 22:45

While crystal frequency stability is nice, only high overclocking will achieve low 'jitter', because powering down the crystal takes many cycles (like, thousands); the high Q of a crystal makes it unsuitable for start/stop operation. High enough crystal frequency (low period time), means the one-cycle response uncertainty to an asynchroous trigger might be acceptable.

Monostables are generally not adjustable over the microseconds-to-milliseconds range. Counters, though, are.

Consider a startable oscillator that comprises an inverting gate feeding a delay line (a foot of CAT-5 wire, four pairs in series, has circa five nanoseconds of delay), would make a low-jitter startable clock, and some programmable counters can generate the events.


simulate this circuit – Schematic created using CircuitLab

Turning the clock off, and waiting for the next trigger, would be the last 'event', and requires only a few cycle times to clear the delay line (damp the reflections in the delay line with its termination resistor).

The hypothetical 5-ns delay line would generate a 100 MHz clock, but that can be divided down to something slower, without compromising phase and timing repeatability.

| improve this answer | |
  • \$\begingroup\$ This could work, it only takes a long PCB trace. I wonder how precise can it be and what’s its temperature coefficient. But, couldn’t I achieve the same thing with a ring (or perhaps a phase delay with capacitors or all-pass stages) oscillator? \$\endgroup\$ – Edgar Brown Mar 16 '19 at 13:50
  • \$\begingroup\$ Temperature effects mainly come from the dielectric, so that's a question for cable manufacturers; phase delays of all sorts can be employed, but resetting the nodes after a trigger isn't as quick if a non-delay-line substitute is used. There are silicon delay line chips, but I've never used them. LTC6994 and DS1100 are such devices. \$\endgroup\$ – Whit3rd Mar 16 '19 at 22:24

So you want a slow linearly-ramping waveform to pass thru a comparator threshold, and have the digital output exhibit exhibit 100nS jitter.

Assume 1 volt per millisecond ramp-rate; that is 0.001 volt per microsecond.

In your preferred 100nanoSec RNS interval, the ramp will ramp by only 100 microVolts.

Thus we now have a computed NOISE FLOOR for the comparator (plus all other random systemic errors) of 100 microVolts, in whatever bandwidth the comparator has internally.

The capacitor you are charging has VERY SLOW BANDWIDTH. The analog comparator is a key jitter-injecting circuit.

The uncertainty of charging current is another.

| improve this answer | |
  • \$\begingroup\$ As I mentioned in the question, what you describe is basically the default implementation. That’s basically why I am asking for a better alternative. A simple 1MHz astable with a counter would already work better, but it will be hard to get below 0.5% error. \$\endgroup\$ – Edgar Brown Mar 16 '19 at 3:49
  • 1
    \$\begingroup\$ OP said a digital input, not a slow ramping analogue input. However, are you familiar with the Oliver Collins paper, 'low jitter hard limiters', which uses a chain of bandwidth limited low noise amplifiers ahead of a conventional comparator to improve dramatically the jitter of a slow ramp into a comparator? \$\endgroup\$ – Neil_UK Mar 16 '19 at 6:40
  • \$\begingroup\$ @ Neil I recall you mentioned that paper several years ago. And I happily read it. Thank you. \$\endgroup\$ – analogsystemsrf Mar 17 '19 at 9:55

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.