To answer your question, you need to understand the difference between how digital circuits work, and how a digital modeling language like Verilog, VHDL, or SystemVerilog (HDL) works. We call it digital circuitry, but really we apply analog voltages/currents to the inputs of analog devices which in turn control the voltages/currents of their outputs. Signals do not go instantaneously from 0 to 1, rather they change from one voltage to another over a finite time. HDLs abstract away all of this analog behavior into discrete events and change signals from 0 to 1 or 1 to 0 instantaneously.
A race condition refers to an indeterminate ordering between the changing of two or more signals. Usually one of the signals is a clock, and the others are data inputs to a flop. If the data changes before the clock, a flip-flip outputs the updated data. If the clock changes before the data, the flip-flop outputs the old data. However in an analog world, change is never instantaneous. The device manufacturer gives you a window of time to guarantee the output. This is called the setup/hold time. If you violate that region, the output can be metastable, meaning they cannot predict the output, and it may even oscillate. Fluctuations in temperatures and voltages within the system can influence the signal change ordering.
In a discrete event simulation, there is always an ordering of signal changes, but the language can only go so far in guaranteeing the ordering depending on how you choose to model it. It's possible to have a race condition in your model, but not in the real design. It's also possible the other way around where you model has a predictable ordering, but the actual design does have race condition. This is because your HDL model does not have an accurate model of physical device delays.
X-propagation is almost an entirely different subject. X is a HDL modeling construct—it is a state that only exists as an abstraction. A real device always has an actual output state even if metastability cannot predict it. The only relevance is some models can choose to output an X state when a setup/hold timing violation occurs.
HDLs have done a poor job in defining how X states get propagated in simulation, many time converting X to a 0 or false state. Formal tools are beginning to address this problem more accurately. But this is too big a topic to answer here.