# What is the difference Verilog race condition, X's propagation and Metastability?

I'm trying to understand Verilog Race Condition X's propagation and Metastability with http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf document.

Because that concept is very confused to understand clearly. So Now I'm trying to make a simple example verilog code to understand their concept. But it's quite a bit difficult.

What is the difference Verilog race condition, X's propagation and Metastability?

So far, from my understanding,

Verilog race condition is when we use blocking assignments in sequential block then blocking assignment execute simultaneously. this is race condition so to prevent this problem, we use non-blocking assignment in sequential block.

always@(posedge clk)
a=b;
always@(posedge clk)
b=a;


Especially, I don't understand about X propagation concept and Metastability concept

From my understanding, X need to be handled by simulator exactly. X need to be propagated to out exactly instead 0 or 1. But so many articles are handled by optimist, a pessimist. So I'm confused this concept what exactly do I need to know this X propagation topic?

So I want to know how to have a test the x propagation at real fields?

• There is no X state in hardware. There are differences in modeling styles how X's propagate. It is not limited to RTL vs. gate-level. But the bigger problem for simulation is there is only X state defined. For example, you cannot subtract X from itself to get 0. Only a formal tool could handle that. – dave_59 Mar 24 at 15:08