I'm trying to understand Verilog Race Condition X's propagation and Metastability with http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf document.

Because that concept is very confused to understand clearly. So Now I'm trying to make a simple example verilog code to understand their concept. But it's quite a bit difficult.

What is the difference Verilog race condition, X's propagation and Metastability?

So far, from my understanding,

Verilog race condition is when we use blocking assignments in sequential block then blocking assignment execute simultaneously. this is race condition so to prevent this problem, we use non-blocking assignment in sequential block.

always@(posedge clk)
always@(posedge clk)

Especially, I don't understand about X propagation concept and Metastability concept

From my understanding, X need to be handled by simulator exactly. X need to be propagated to out exactly instead 0 or 1. But so many articles are handled by optimist, a pessimist. So I'm confused this concept what exactly do I need to know this X propagation topic?

So I want to know how to have a test the x propagation at real fields?

enter image description here

Add for understanding about X-propagation


1 Answer 1


To answer your question, you need to understand the difference between how digital circuits work, and how a digital modeling language like Verilog, VHDL, or SystemVerilog (HDL) works. We call it digital circuitry, but really we apply analog voltages/currents to the inputs of analog devices which in turn control the voltages/currents of their outputs. Signals do not go instantaneously from 0 to 1, rather they change from one voltage to another over a finite time. HDLs abstract away all of this analog behavior into discrete events and change signals from 0 to 1 or 1 to 0 instantaneously.

A race condition refers to an indeterminate ordering between the changing of two or more signals. Usually one of the signals is a clock, and the others are data inputs to a flop. If the data changes before the clock, a flip-flip outputs the updated data. If the clock changes before the data, the flip-flop outputs the old data. However in an analog world, change is never instantaneous. The device manufacturer gives you a window of time to guarantee the output. This is called the setup/hold time. If you violate that region, the output can be metastable, meaning they cannot predict the output, and it may even oscillate. Fluctuations in temperatures and voltages within the system can influence the signal change ordering.

In a discrete event simulation, there is always an ordering of signal changes, but the language can only go so far in guaranteeing the ordering depending on how you choose to model it. It's possible to have a race condition in your model, but not in the real design. It's also possible the other way around where you model has a predictable ordering, but the actual design does have race condition. This is because your HDL model does not have an accurate model of physical device delays.

X-propagation is almost an entirely different subject. X is a HDL modeling construct—it is a state that only exists as an abstraction. A real device always has an actual output state even if metastability cannot predict it. The only relevance is some models can choose to output an X state when a setup/hold timing violation occurs.

HDLs have done a poor job in defining how X states get propagated in simulation, many time converting X to a 0 or false state. Formal tools are beginning to address this problem more accurately. But this is too big a topic to answer here.

  • \$\begingroup\$ About X-propagation, as I understand from your answer, I can conclude that HDL vs real hardware's X simulation would be different. most common way for checking the difference between their result, we compare between HDL and Gate-Level Simulation. Am I understand correctly ? \$\endgroup\$
    – al01
    Mar 24, 2019 at 14:30
  • 3
    \$\begingroup\$ There is no X state in hardware. There are differences in modeling styles how X's propagate. It is not limited to RTL vs. gate-level. But the bigger problem for simulation is there is only X state defined. For example, you cannot subtract X from itself to get 0. Only a formal tool could handle that. \$\endgroup\$
    – dave_59
    Mar 24, 2019 at 15:08

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