The product naming for ARM cores captures in effect 3 different things:
- Processor Architecture
- Performance and feature level (roughly)
- Target market.
In the old days (pre ~2004), there were ARM7 (microcontroler), ARM9 (mid range) and ARM11 (high performance). These came in different configurations with different features, but the detail is fairly old now.
Cortex-A5 was the first of the ARMv7-A architecture. These can be seen as an evolution of the ARMv6 architecture, mostly compatible but with more features.
Cortex-M3 was the first of the ARMv7-M architecture. This was a step-change, with a different exception model, and only supporting Thumb state (16/32 bit instruction set).
Cortex-R4 was the first real-time optimised ARMv7-R processor.
Cortex-M0 was the first of the ARMv6-M architecture (which is a subset of ARMv7-M, not related to ARMv6).
For ARMv8 variants, double digit numbering was used (Cortex-A15 is an exception, being ARMv7 still).
Between ARM11 and Cortex-A5, not a huge difference (except in much of the low level detail).
Between ARM7 and Cortex-M3, quite some big changes, particularly the instruction set, and the memory model.
Between Cortex-A7 and Cortex-A53, another instruction set (A32/A64).
Another significant difference that came about with the switch to ARMv7 (and the Cortex name) is the introduction of an asynchronous debug interface. ARM7/ARM9 used a JTAG tap embedded in the processor. Later designs used a CoreSight debug port as a path to access memory-mapped debug registers. This removed the notorious RTCK signal, and allowed the introduction of SWD as a debug interface.