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On many MCUs, pin-states default to tri-stated (a.k.a. analog inputs) when the MCU resets so as to not affect the circuits they are connected to until software configures the pins. The tri-stated pins also allow the HW designer to choose the pull state of each pin on a case-by-case basis in function of the underlying circuitry.

However, there are some MCUs (and SoCs) that default their pins to instead activate an internal pull-up/down. For example, the LPC845 defaults all pins to pull-ups coming out of reset. LPC845 Datasheet Section 8.11.1

Is there a reason defaulting pins to pull-up/down is preferable to tri-stated (other than the possible incremental power savings when coming out of a reset, or the marginal BOM cost savings)?

If anything, I rarely find that pins should be pulled-up coming out of reset (I typically need to pull them down, if at all).

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    \$\begingroup\$ I'd probably want that behavior to be configurable with fuses for the device, during programming. That's my thought, right now. \$\endgroup\$
    – jonk
    Mar 19, 2019 at 5:47
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    \$\begingroup\$ Sounds like a good chip. The real question is why the vast majority of MCUs leave them in tri-state/inputs, exposing the pins to EMI and ESD during MCU boot-up. Because we all like EMC tests failing and ESD-damaged ICs, right? \$\endgroup\$
    – Lundin
    Mar 19, 2019 at 12:55
  • \$\begingroup\$ @Lundin This is an interesting point. I could see EMI being an issue if the pins are not externally pulled, but how would ESD be mitigated by defaulting pins to a certain pull state coming out of reset? Aren't the input pin diodes sufficient? \$\endgroup\$
    – TRISAbits
    Mar 19, 2019 at 17:20
  • \$\begingroup\$ @TRISAbits On modern MCUs the diodes should hopefully be ok... maybe. There's often no public spec on them. So it is good practice to have some manner of resistor between the pin and connectors/buttons/stuff that humans might poke at. \$\endgroup\$
    – Lundin
    Mar 20, 2019 at 8:50

5 Answers 5

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Because it's good practice to never leave logic pins purely floating.
Brief TI Overview
Detailed TI overview
Amusing dramatized war story of a real-world example

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  • \$\begingroup\$ I completely agree. Floating pins are indeed a bad thing for power consumption. But any well behaved firmware should set all unused pins to a known state, so the power loss would only occur coming out of a reset (and this loss can be eliminated by placing external pulls). So is the idea that by giving a default state to a pin (pull-up/down) the FW needs less massaging to get lower power numbers? \$\endgroup\$
    – TRISAbits
    Mar 19, 2019 at 6:19
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    \$\begingroup\$ I think you've cut to the heart of the matter here. If the firmware is well-behaved and/or the hardware designer had the good sense to apply proper pull-ups or pull-downs, then there would be absolutely no need for this type of initialization. And I'd guess that's why not all chip designers do this. It's all a matter of philosophy -- do you want to presume your users are smart enough to do The Right Thing, or do you want to protect them if they don't? It could be argued either way... \$\endgroup\$
    – Mr. Snrub
    Mar 19, 2019 at 6:22
  • \$\begingroup\$ Certain MCUs have their digital input buffer logic disabled coming out of reset (e.g. PIC12/16/18), which presumably is intended to prevent leakages caused by shoot-through? If so, that would be an alternative to forcing pins in a certain known-state. \$\endgroup\$
    – TRISAbits
    Mar 19, 2019 at 15:58
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    \$\begingroup\$ BTW, you mentioned leakage currents, but as illustrated in the "amusing dramatized war story", my bigger worry would be oscillations. Leakage currents will go away once the FW sets the pin to a good state, but if a floating pin oscillates then there is the danger of it causing the logic to go into an invalid state. \$\endgroup\$
    – Mr. Snrub
    Mar 19, 2019 at 18:49
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    \$\begingroup\$ I really mean to say that oscillation on an input pin at any time, whether in reset or not, is probably Bad News. Yes if the oscillation occurred during the reset process, then I would be gravely concerned that the reset process may not fully initialize things to a known good state. \$\endgroup\$
    – Mr. Snrub
    Mar 19, 2019 at 19:49
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Other answers have given general reasons why a chip maker might make the choice to enable pull-ups by default. However, in the specific case of LPC845, there is an additional reason: it has specialized FAst Initialization Memory (FAIM) that can be used to set the state immediately after reset:

The FAIM contents provide a user-programmable initial configuration for aspects of the microcontroller, which take effect immediately after reset, before code begins to run. For instance, the standard I/O pads normally come out of reset with the internal pull-ups enabled. In some systems this may cause excess current to flow, until software can reconfigure the pads. However, by programming the FAIM appropriately, every pad's reset configuration can be customized.

(LPC84x user manual section 4.2)

Thus they've chosen the safe (from power usage and EMI point of view) default, while allowing more advanced users to customize the setting.

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  • \$\begingroup\$ The downside with the FAIM is that it requires an additional programming step to set it up front, which means that your design should survive the incorrect pull-state until the FAIM is updated. Alternatively you can install a stronger external pull to overdrive the default internal setup, but you've now introduced a perpetual power loss through the external pull. I guess you can't have your cake and eat it too. \$\endgroup\$
    – TRISAbits
    Mar 19, 2019 at 15:54
  • \$\begingroup\$ @TRISAbits Yeah. But after all even if it were tristated, you'd need the external pulldown on important pins, and if it is pulling to the default state, the average loss is not so much. \$\endgroup\$
    – jpa
    Mar 19, 2019 at 20:31
  • \$\begingroup\$ The point I was (poorly) making is that the external pull will have to be stronger than otherwise required in order to overdrive the internal pull. If the pins were tri-stated then the pull could be weaker, which would result is less power loss through the external pull. \$\endgroup\$
    – TRISAbits
    Mar 19, 2019 at 22:20
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Back in the days there were Intel 8051 microcontrollers that only had open drain I/O pins, so most of the time you needed external pull-ups anyway to do useful things like connecting to pushbuttons or controlling CMOS inputs of other chips. This is most likely to have easy redesign of such boards with a modern microcontroller, or people from that era that are accustomed to designing with pulled-up open-collector I/Os. Back in the day, you mostly needed pull-ups if anything, and rarely pull-downs.

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  • \$\begingroup\$ That's a really interesting bit of insight, and explains why a lot of logic chips have active-low output-enable pins. Active-high logic doesn't mesh as well when the default pull-state is high. As an aside it also doesn't mesh well when directly connected to the gate of a NMOS, unless you want the transistor to turn on by default. \$\endgroup\$
    – TRISAbits
    Mar 19, 2019 at 16:10
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    \$\begingroup\$ Also other chips of that era have active signals when low. TTL chips (74XX and 74LSXX series for example) can pull low stronger than push high. Therefore fast falling edge is sharper and more defined than slow exponentially rising edge. Also small currents flow in and out of chip inputs as they are not so high impedance. Therefore, pull-ups are sometimes necessary, and pull-ups can be weaker than pull-downs, so that's why you have active low logic with pull-ups, with pushbuttons grounding the inputs and outputs turning on LEDs by grounding the LED via resistor. \$\endgroup\$
    – Justme
    Mar 19, 2019 at 19:39
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Leaving GPIO pins as tri-stated inputs have many undesirable effects:

  1. As manufacturing process has certain variance and a lot of other circuitry is connected to GPIO (as output buffer and ESD protection), direction of resulting parasitic leakage is unpredictable, so the state can take either logic high or low;

  2. Again, due to process variation and temperature dependence, the pin leakage can be very small, resulting in either very slow change of logic state after, say, several minutes, which might be a challenge to accommodate in code, or it can drift in unpredictable direction.

  3. Leaving pins floating might lead to establishing some middle potential, where the pin input buffer may act as linear amplifier with substantial gain, causing either self-oscillations (due to parasitic positive feedback across power rails), or be susceptible to external electromagnetic interference. Oscillations can be somewhere internally, and lead to out-of range power consumption.

4... must forget something else... power-on transients?

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From a systems point of view, having the pins start in a defined state is a benefit. For example, a motor might be attached that shouldn't be activated without command. Peripherals usually expect their interfaces to be in a certain state, and starting in high-Z may not provide the required state. As the internal pull ups/downs in a typical microcontroller are relatively weak, they may be overridden by a stronger external pull up/down where required. As an additional note, it is nice to see in the datasheet what the expected behaviour of the pins is, this is sometimes not included..!

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    \$\begingroup\$ The problem with providing an external pull-up when an internal one is enabled is two-fold: [1] The external pull has to be properly sized to be far stronger (good rule of thumb is at least 10x). Otherwise you will create a voltage divider, which can set the voltage into that middle no-mans-land zone. [2] The stronger external pull introduces a continuous power loss (if the pin state is frequently opposite the pull direction), which will quickly consume more power than any loses from having tri-stated pins out of reset. \$\endgroup\$
    – TRISAbits
    Mar 19, 2019 at 16:05
  • \$\begingroup\$ @TRISAbits Agreed on both points. Not that desirable to override, but most internals are 50-100K so not disasterous. Read the manual, as ever :) \$\endgroup\$
    – awjlogan
    Mar 19, 2019 at 16:20
  • \$\begingroup\$ @TRISAbits And also it's not about power in this example, it's about how the wider system interacts at reset, not just the MCU. \$\endgroup\$
    – awjlogan
    Mar 19, 2019 at 16:29

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