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Why do certain ICs like 74ALS174 use an inverter so as to make a Positive-going clock transitions occur instead of Negative-going ? Why can't we just save expense of an inverter by removing it and allowing the more natural Negative-going clock transitions? (CP in image)

enter image description here

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    \$\begingroup\$ I suspect that it is partially the whim of the original designer, and then after that everyone selling the chip was locked into the pin-for-pin compatibility. The other part is because if there's internal fan-out (as there is here) you'd want to buffer the incoming signal, and an inverter is cheaper than a buffer. (In most logic families, a buffer is just a cascaded pair of inverters). \$\endgroup\$ – TimWescott Mar 19 '19 at 16:23
  • \$\begingroup\$ It is also convention - the majority (maybe all) D-type registers are positive edge triggered for all types of device and manufacturers so it is desirable that the device is positive edge triggered at the pin. However the internal design is not constrained and it may be better to be negative edge triggered internally. It will also affect setup and hold times - these days a zero hold time is desirable, the clock buffer delay may help that. \$\endgroup\$ – Kevin White Mar 19 '19 at 16:30
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    \$\begingroup\$ Tut, tut, @Tim. Comments are for clarification. You've written a good answer. Move it into an answer. \$\endgroup\$ – Transistor Mar 19 '19 at 16:31
  • \$\begingroup\$ @Transistor it was the leading "I suspect" that was holding me up. \$\endgroup\$ – TimWescott Mar 19 '19 at 17:58
  • \$\begingroup\$ I'd guess the main reason for positive or negative clocks would probably have more to do with the fundamental logic (NAND / NOR) used to implement the flip-flop, rather than designer whim. \$\endgroup\$ – StainlessSteelRat Mar 19 '19 at 18:54
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Note that in the specific example of the '174 that you show, the flip-flops themselves are shown with inverted clock inputs (falling edge), so the net effect of the inverting buffer is to make the chip overall work on the rising edge of the clock.

As Tim Wescott mentioned in a comment, this sort of detail is normally related to the internal implementation technology. The only thing you care about when using the chip is the behavior relative to the signals at the pins.

As a historical oddity, D flip-flops normally work on the rising edge, because that's how most users prefer to think about their data registers. But J-K flip-flops normally work on the falling edge. That's because they were often used to build ripple counters (tie the J and K inputs high to create a T flip-flop) and you want the next-more-significant bit to toggle on the falling edge of the previous bit. In general, you'll find that ripple counters ('90, '92, '93, etc.) work on the falling edge, while synchronous counters ('160, '161, '162, '163, etc.) generally work on the rising edge. This allows both types to be easily cascaded with themselves.

But in the end, there's no technical reason to pick one convention over another. There's nothing "more natural" about either one — it's just an arbitrary choice.

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I suspect that it is partially the whim of the original designer, and then after that everyone selling the chip was locked into the pin-for-pin compatibility. The other part is because if there's internal fan-out (as there is here) you'd want to buffer the incoming signal, and an inverter is cheaper than a buffer. (In most logic families, a buffer is just a cascaded pair of inverters).

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