I'm simulating voltage multipliers (Dickson topology) with the stages from 1 to 12, following the paper "Design Optimization and Implementation for RF Energy Harvesting Circuits, 2012". The load was fixed at 15 kOhm.
What made me confuse was that, in my simulation results, the output voltage was lower at low Pin (input RF power) when the stage increased, although it was higher with higher Pin. And the power conversion efficiency (PCE = Pdc/Pin x 100%) was decreased. I attached my simulation results for the comparison.
In the paper I mentioned, they intended to design a system that the output voltage reached 1.8V at Pin = -20 dBm (?). And they got this by parallel connection of 2 circuits, one with 7 stages and one with 10 stages. Their efficiency is higher with more circuits (file attached).
Could anyone get the multiplier results the same as that of the paper? I tried using different matching topologies and values, but the results are still the same trend: decreasing with higher stages!