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I'm simulating voltage multipliers (Dickson topology) with the stages from 1 to 12, following the paper "Design Optimization and Implementation for RF Energy Harvesting Circuits, 2012". The load was fixed at 15 kOhm.

What made me confuse was that, in my simulation results, the output voltage was lower at low Pin (input RF power) when the stage increased, although it was higher with higher Pin. And the power conversion efficiency (PCE = Pdc/Pin x 100%) was decreased. I attached my simulation results for the comparison.

enter image description here

In the paper I mentioned, they intended to design a system that the output voltage reached 1.8V at Pin = -20 dBm (?). And they got this by parallel connection of 2 circuits, one with 7 stages and one with 10 stages. Their efficiency is higher with more circuits (file attached).

enter image description here

Here is my results enter image description here

Could anyone get the multiplier results the same as that of the paper? I tried using different matching topologies and values, but the results are still the same trend: decreasing with higher stages!

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  • \$\begingroup\$ There are long, drawn-out papers published about variation vs number of sections, etc. It's a well-covered topic, I think. Have you tried to find any of the published discussions? I think I've got Ph.D. Theses, chapters in books, IEEE transactions articles, and gobs of such white papers (files) stored on my machine. Maybe a dozen or more. Not hard to find, really. \$\endgroup\$ – jonk Mar 20 '19 at 3:06
  • \$\begingroup\$ Did you optimize the capacitor ratios? I believe you have multiple interacting capacitive dividers the more stages you add. \$\endgroup\$ – Edgar Brown Mar 20 '19 at 4:11
  • \$\begingroup\$ Is there some obvious difference between your circuits and the circuits in the paper? \$\endgroup\$ – JRE Mar 20 '19 at 6:43
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    \$\begingroup\$ The devil's in the detail - show your circuit. \$\endgroup\$ – Andy aka Mar 20 '19 at 9:15

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