I am trying to interface an IC with an FPGA. Both the IC & FPGA run at 66 MHz with no clock skew between them and the propagation delay of the data lines is negligible, since the length of the PCB traces that connect the 2 chips is very short.
The IC has a setup time 1 ns and hold time 4.8 ns, while the sampling of the data is performed at the rising edge of the clock.
According to the I/O Timing Analysis report of the FPGA software, which is created after the Place & Route so I assume is the absolute final report, I have a Clock to Output delay of around 10 ns.
If the FPGA outputs data at the rising edge with the system clock period being 15 ns and the clock-to-output delay 10 ns, new data have arrive 3 ns before the required setup time so I respect the setup time, which is 1 ns. At the same time, in the next cycle, since the clock to output is 10 ns, the new data will become available after 10 ns, so I have respected the hold time as well, which is 4.8 ns.
Is my reasoning correct?
Thanks in advance.
FPGA is MachXO2 by Lattice (TQFP-144) while the IC in question is FT601 by FTDI, which is USB 3.0 to FIFO Bridge. Since clock-to-out is 10 ns, and the next output will become available when the rising edge comes, I assume to have a hold time of 10 ns (5 ns before the rising edge arrives plus 10 ns after the rising edge, which is the clock-to-output delay, totaling 15 ns).