# PLL placing fails on Lattice 5LP1K

I have a board with a Lattice ICE40 5LP1K FPGA that does some small jobs like handling communication protocol and some IOs. My problem is that I cannot compile the project as the IceCube tells me

I2709: Tool unable to complete IOPlacement for the design
E2694: PLL: pll_inst.pll_pll_inst could not be placed
E2693: PLL placement is infeasible for the design


I'm using a PLL of type SB_PLL40_2F_CORE

Now if I free up the global buffer G0 PIOT_46B (exclude it from the pin assignment file) everything works fine. So I assume the PLL requires a global buffer to be placed, but I'm using pin PIOT_46B as a normal LVCMOS IO, does this also occupy the global buffer? My Clock is on PIOB_3b.

Freeing up any other global buffer pin doesn't solve my problem, it has to be this specific one as it seems.

I further found some information that it would may help to use SB_PLL40_2F_PAD instead of _CORE but that's only supported for clock inputs on bank0 or 2 but mine is placed on bank3.

Is there any solution/explanation for this issue or do I have to change my board routing to be able to free up PIOT_46B?

Edit It appears that only inputs are not supported, if I define PIOT_46B to be an output the design can be synthesized. But so far I don't understand the phenomenon.

• I'd look at the routing map if the lattice software generates one, odds are your running out of some global resource like a wire because there are too many signals using global resources and it's trying to route the PLL signal on the global wires that are connected to all the blocks. – laptop2d Mar 21 at 15:01
• It generates a placer output file but I don't know if that contains any useful information regarding my issue. What I figured out according to PLL User Guide is that it works if PIOT_46b is used as an output.I just don't understand what all my GBs are used up for... – Humpawumpa Mar 25 at 7:53
• Here's the correct document link PLL User Guide – Humpawumpa Mar 25 at 8:00
• Someone ever faced the same issue? If I know there's nothing I can do about it I at least know that I have to change my PCB. – Humpawumpa Mar 26 at 8:11

## 1 Answer

I remember that I had some trouble with the PLL instantiation (SB_PLL40_CORE) for a ICE40UL1K-CM36A. IIRC it was the combination of "which input and output to use". In my case the solution was to avoid PLLOUTCORE and use PLLOUTGLOBAL instead. I think I let the tool decide where to place the clock and locked that pin (F2) later.

So my recommendation: check if different combination of CORE vs GLOBAL make any difference if this does not help let the tool decide where to place the clkin pin. Maybe you are lucky and there is another pin which is not G6 and the tool is fine with.