I have a board with a Lattice ICE40 5LP1K FPGA that does some small jobs like handling communication protocol and some IOs. My problem is that I cannot compile the project as the IceCube tells me
I2709: Tool unable to complete IOPlacement for the design E2694: PLL: pll_inst.pll_pll_inst could not be placed E2693: PLL placement is infeasible for the design
I'm using a PLL of type
Now if I free up the global buffer G0
PIOT_46B (exclude it from the pin assignment file) everything works fine.
So I assume the PLL requires a global buffer to be placed, but I'm using pin
PIOT_46B as a normal LVCMOS IO, does this also occupy the global buffer?
My Clock is on
Freeing up any other global buffer pin doesn't solve my problem, it has to be this specific one as it seems.
I further found some information that it would may help to use
SB_PLL40_2F_PAD instead of
_CORE but that's only supported for clock inputs on bank0 or 2 but mine is placed on bank3.
Is there any solution/explanation for this issue or do I have to change my board routing to be able to free up
Edit It appears that only inputs are not supported, if I define
PIOT_46B to be an output the design can be synthesized. But so far I don't understand the phenomenon.