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I am trying to exercise the communication between AXI4 master and slaves over the Chip2Chip IP core. When I have a master in one design and the slaves in the other, everything works fine - I properly access both slaves as shown below. However, if I add an identical slave into the design with the master, the master can not access the slaves of the other design. The PG067 on page 5 says that "The AXI Chip2Chip Master instance provides an AXI4 slave interface that can be directly connected to AXI Master or AXI interconnect devices." So, having an interconnect is ok. This design works: enter image description here Here's what does not seem to be working enter image description here

Questions:

  1. Why having an interconnect and a slave in the master design stops working? I would expect that something is missing in the axi communication. Additional signals?
  2. If I had two slaves with identical addresses, one in design1 and another in design2, how would the master (or interconnect) know which one to access? Would this be even legal, or the designer must ensure that both designs have slaves with unique addresses?
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  • \$\begingroup\$ How are you connecting the Master, Interconnect, and "BRAM Controller 0xC0000000" in your bottom image? The interconnect should be the only slave interface connected to the master. Then the BRAM controller and Chip2Chip master would be connected to the interconnect. \$\endgroup\$ – Kevin Kruse Mar 22 at 12:51
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    \$\begingroup\$ @KevinKruse The bottom diagram should be more explicit now. \$\endgroup\$ – Nazar Mar 22 at 12:59
  • \$\begingroup\$ Both diagrams are correct. There was a problem with addressing. \$\endgroup\$ – Nazar Mar 22 at 17:01
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I don't know much about chip2chip, but you have to make sure the AXI interconnect is routing things to the correct master interface. You can't have address collisions as this becomes ambiguous. You also need to make sure the ID fields are properly turned around so the responses are sent to the correct master. It sounds like you may have some sort of address configuration issue. If you move the slaves over to the first FPGA and connect everything in exactly the same way just without the chip2chip link, does it work or does it still fail?

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  • \$\begingroup\$ Yes, the addressing was incorrect. \$\endgroup\$ – Nazar Mar 25 at 12:15

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