I am trying to exercise the communication between AXI4 master and slaves over the Chip2Chip IP core. When I have a master in one design and the slaves in the other, everything works fine - I properly access both slaves as shown below. However, if I add an identical slave into the design with the master, the master can not access the slaves of the other design. The PG067 on page 5 says that "The AXI Chip2Chip Master instance provides an AXI4 slave interface that can be directly connected to AXI Master or AXI interconnect devices." So, having an interconnect is ok. This design works: Here's what does not seem to be working
- Why having an interconnect and a slave in the master design stops working? I would expect that something is missing in the axi communication. Additional signals?
- If I had two slaves with identical addresses, one in design1 and another in design2, how would the master (or interconnect) know which one to access? Would this be even legal, or the designer must ensure that both designs have slaves with unique addresses?