I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform read and write simultaneously, I thought about using a faster clock and give 1 cycle for read another cycle for write, but that option is not preferable, in the context of my project. There is the idea of making a system with priority for read however I am not sure how to manage the write request. If I give priority to read I might lose some write requests as well.


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    \$\begingroup\$ The question is not clear. Single port RAM can't perform simultaneous read and write by definition. \$\endgroup\$ – Eugene Sh. Mar 22 '19 at 16:02
  • \$\begingroup\$ The question in short is , in order to save some space , how to make use of an on chip single port ram and use it as a synchronous FIFO. Thats the challenge being not able to read and write simultaneously into the Single Port RAM \$\endgroup\$ – Hachani Ahmed Mar 22 '19 at 16:16
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    \$\begingroup\$ Either use a single port RAM and make an arbiter to handle simultaneous read/write requests, or use a dual port RAM. You can't have the best of both worlds. \$\endgroup\$ – Kevin Kruse Mar 22 '19 at 16:29
  • \$\begingroup\$ Yes , I thought about implementing an arbiter that gives a priority to read operations, however , I have a confusion: If I give priority a priority read, how can I manage the write part, should I keep the data to be written into a buffer or just disregard them ? and vice versa \$\endgroup\$ – Hachani Ahmed Mar 22 '19 at 17:19
  • \$\begingroup\$ depth of the buffer should be designed wisely as well, depending on read and write rates \$\endgroup\$ – Mitu Raj Apr 16 '19 at 6:46

You need to define your requirements more carefully.

  • How many reads can occur on contiguous clock cycles?

  • How many writes can occur on contiguous clock cycles?

If the answer to both is "just one", then all you need is a simple aribter. Do the read when requested, and if a write happens at the same time, hold it in a register until the next clock cycle — which is guaranteed to be available.

If reads or writes can occur in larger "bursts", then things get quite a bit more complicated, and you might as well bite the bullet and put in a true dual-port memory, or clock your single-port memory at twice the speed.

  • \$\begingroup\$ thanks @dave , this give me more ideas, I do have 1 read that happen within 14 cycles , the read takes 2 cycles , due to the RAM latency . and then I will be having 2 or 3 writes with 14 cycles. Using dual port ram, or having a faster clock would solve my problem , but they are 2 options that I can not use in the context of my project. \$\endgroup\$ – Hachani Ahmed Mar 22 '19 at 18:32

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