I'd like to build a queue of three internal bits as inexpensively as possible. Externally, the queue has two input bits and one output bit. The inputs are (dataIn) and (shift), and the output is (dataOut). The internal bits are arranged from the left to the right, and can be implemented in any way imaginable, as long as it's as inexpensive as possible. In my mind's eye I'm thinking of something like a DRAM, where there's just one transistor/capacitor pair per each bit, but I don't know if that's possible.

The output (dataOut) always has the value of the internal bit on the right. While (shift) is low, all three internal bits just retain their current value. When (shift) goes high, the internal bit on the left takes the value of (dataIn), the internal bit in the middle takes the former value of the bit on the left, and the internal bit on the right takes the former value of the bit in the middle.

In particular, I'm interested in whether or not this can occur with just three internal bits, or whether instead each bit has to have a master (set on one edge of changing (shift)) and a slave (set from the value of the master on the other edge).

Also, a size of three is just a fairly simple example of what I want to have; ultimately my design is going to need much larger groups of internal bits.

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    \$\begingroup\$ How many of these systems do you need? The answer will be different if you're building 10 of them vs building 10 million of them. \$\endgroup\$ – The Photon Mar 22 '19 at 20:37
  • \$\begingroup\$ you're right, but i think he is talking about design options for now, the manufacture scale is not still being argued \$\endgroup\$ – Hamed Temsah Mar 22 '19 at 20:44
  • \$\begingroup\$ I see that an ON semiconductor MC74HC595 can be purchased for 28 cents. It gets you 8 bits of shift register in a straightforward solution. Do you need a significantly lower cost? \$\endgroup\$ – George White Mar 22 '19 at 22:29
  • \$\begingroup\$ The Photon posted, "How many of these systems do you need? The answer will be different if you're building 10 of them vs building 10 million of them." The prototype I'm thinking of building will have precisely 30,182,209,528 bits. To be perfectly honest, I don't need any three-bit queues at all. That prototype will have 143 queues, each of which's size will be a power of two, ranging from two to the zero (1) to two to the 24 (16,777,216), and each element of each queue will be a 257-bit value, not a single bit. \$\endgroup\$ – KevinSim Mar 23 '19 at 19:24
  • \$\begingroup\$ But it seemed to me that the crucial question is whether I can implement each bit in the three-bit shift register inexpensively, because if my end product is ten times as expensive as a computer with similar size, then I may have to seriously rethink its marketability. \$\endgroup\$ – KevinSim Mar 23 '19 at 19:25

Your description reads, in part, "when (shift) goes high ..." — this describes edge-triggered behavior, so yes, you need master-slave flip-flops to hold the internal bits.

You can also do something like this using dynamic logic, where each stage consists of a capacitor, a buffer and a transmission gate. This would be driven by a 2-phase (non-overlapping) clock. But it still requires two such stages for each "bit" of storage.

But if all you're looking for is a large FIFO buffer, then an actual shift register is not the preferred implementation. Instead, use a block of RAM (either SRAM or DRAM, with the understanding that DRAM will also require refreshing) along with a pair of counters to keep track of the current write ("head") and read ("tail") addresses. Increment the counters to logically "shift" the data.

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