I have incorporated a reference design from this page on discrete driver circuits for vibration motors for the high-side configuration.

Here is the picture of the circuit: enter image description here

I'm concerned about the fact that my VDD, which is driving the motor is 3.0V, and my PWM output voltage from a microcontroller is 3.3V. Would there be any damage caused by the reverse current when the PWM output is high?

My pull-up resistors and gate resistors are 10k each. The 3.0V comes from a buck converter, and I can't find any absolute maximum rating specification in the datasheet for the IC that I'm using about reverse current. This is the datasheet for the IC in particular. Should I add a diode with a forward voltage of ~0.3V? Thoughts?

  • \$\begingroup\$ can't you use a voltage divider on the PWM output to bring it down to 3.0V? \$\endgroup\$
    – xuva
    Mar 23, 2019 at 19:33
  • \$\begingroup\$ What I had thought of initially was a diode with a forward voltage drop around 0.3V. But I have laid out the PCB before realizing this fact, so would rather not add too many components due to lack of space \$\endgroup\$
    – Lim LS
    Mar 23, 2019 at 19:58

1 Answer 1


You should probably have a lower value series gate resistor. Maybe 1K and 47K or so is fine for the gate-source resistor.

When the PWM output goes high (assuming it goes to approximately Vdd) the transistor switches off fairly quickly (depending on the gate series resistor, gate charge and drive capability of the chip). The drain of the P-channel mosfet goes negative a few hundred mV as the motor peak current now flows through the Schottky rather than the transistor.

The only danger is that the switching regulator may react to the sudden removal of the heavy load by overshooting, and that overshoot may result in excessive voltage on the 3V rail, possibly damaging something. So you want have adequate capacitance on the rail that it will not excessively overshoot. From the datasheet you can see the response to transient loads:

enter image description here

Note that they've beefed up the output capacitor to 22uF from the 10uF shown in the typical schematic. Also note that ceramic capacitors often have a very high voltage coefficient, so you may need two or three times the nominal capacitance to get a real 22uF. If you have the room, I would suggest 47uF electrolytic in parallel with 10uF ceramic, forming as small a loop as possible.

There is a bit of a trade-off with the series gate resistor. 10K will give very low switching speed, so a lot of switching losses. Something like 10 ohms will give very fast switching but may cause additional problems with stray inductance (which could couple back to the chip through the gate capacitance). What is best is to trade off against the gate capacitance of your particular MOSFET and your proposed PWM frequency.

To answer your specific question, there is no inherent problem in the gate voltage going above the source voltage (provided it stays withing the Vgs rating of the MOSFET). Once it goes above Vdd - Vgs(th) very little current flows. Just don't exceed Vdd + Vgs(max) under any conditions, even momentarily.

The only purpose of the pullup is to make sure the transistor turns off if the driver or connections goes open, so 50K or 100K is typically fine, it only has to switch once, if that, normally.

  • \$\begingroup\$ Thanks for showing which part of the datasheet to look at in this case. As per your suggestion, I've switched the gate resistor value to 1k. What I was initially concerned about was current going from the PWM pin through the pull-up resistor to the VDD node. For the capacitors, what is the logic of having an electrolytic in parallel with the ceramic? \$\endgroup\$
    – Lim LS
    Mar 23, 2019 at 19:56
  • \$\begingroup\$ @LimLS I don't see that small amount of current (smaller now with a 47K resistor) being a problem. It's only 6uA. It will disappear into the other loads or the regulator output divider. The electrolytic provides high capacitance cheaply but has high ESR so fast pulses can get through. The ceramic has lower capacitance but very low ESR so it handles the higher frequencies. \$\endgroup\$ Mar 23, 2019 at 19:58

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