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I have been wokring on a circuit, where I am amplifying a signal to a high voltage(around 100V) with a frequency of 20kHz but with fast edges. `

The op-amp shown below is used as inverting amplfier thus for the feedback loop. I am using the AD712.

I want to make sure I get the PCB layout correct, so I have been spending a lot of time on reading application regarding PCB layout. There is one point I stumbled on ; In this article https://medium.com/@Altium/designing-operational-amplifiers-pcb-layout-tips-to-reduce-the-noise-e4900a7d7fc5 it is stated that having a ground near the input pins causes stray capacitance which can lead to instability. On the other hand, I know also that it is not good practice to break the ground plane.

so, what is the best way to go about this?Should I break the ground plane close to the inputs of the op-amp? Does someone have experience with this?

enter image description here

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  • \$\begingroup\$ To reduce stray capacitance people use local voids in ground plane under pads and even components that may be sensitive to parasitic capacitance. \$\endgroup\$ – Ale..chenski Mar 24 '19 at 1:33
  • \$\begingroup\$ So local voids only at the inputs of the op-amp? what kind of components are you refering to? \$\endgroup\$ – Navaro Mar 25 '19 at 22:24
  • \$\begingroup\$ I am referring to pads for surface-mount resistors connected to these inputs. \$\endgroup\$ – Ale..chenski Mar 25 '19 at 22:42
  • \$\begingroup\$ So by using larger resistors instead of smaller resistors you could effectively reduce the stray capacitance? \$\endgroup\$ – Navaro Mar 25 '19 at 23:41
  • \$\begingroup\$ Larger resistors have larger pads. Larger pads have more capacitance to ground layers. \$\endgroup\$ – Ale..chenski Mar 26 '19 at 1:11
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The need to reduce the C_virtual_ground (Vin-) capacitance depends on the total phaseshift of the feedback circuit. For low values of resistance, the capacitance can be huge and the circuit still has no peaking. For high values of resistance (in the simulation below, I used gain of 10x, with 1Meg input R and 10Meg feedback R), the C_virtground and the phaseshift of Cload and Rout, and the opamp's phase_margin, all contribute to peaking.

When these 3 causes of phaseshift sum to near 90 degrees, expect massive peaking.

Again ---- low values of Rfb make everything operate without peaking,

And many circuits that should peak ---- do not --- because of stray capacitance (stray electric field coupling) across the two PCB pads of the Rfeedback resistor. Notice the SMT resistors likely have much more of this lead-lead coupling than will axial feedback resistors. Thus the SAME opamp, using the SAME value of resistors, will have the PEAKING determined by the choice of resistor package: SMT or axial.

In addition to resistor values and parasitic C across the resistor PCB SMT pads, the opamp's differential_mode Cin (Miller Effect can be a killer) will matter. And as you already know about, the VirtualGround node (Vin-) capacitance.

Here is a 45MHz opamp (MCP655) modeled with 3pF on the virtualground node, Rin of 1,000,001 ohm and Rfb of 10 Million Ohms.

Notice the 20dB peaking at 500,000Hz. And notice NO parasitic C across Rfb.

enter image description here

Your opamp will have finite phase margin, often included in the datasheet. This, the phase margin, is characterized (tho not likely being production tested) at Unity Gain Bandwidth. If you have gain of 10X, then divide that by 10; if you have gain of 100X, then divide by 100; this works because for small angles (in radians), the angle is approx. tangent(angle) is approx. sin(angle). Thus if you have 45 degrees phase margin, and you have gain of 10, then the opamp contributes another 4.5 degrees phase shift (assuming ONE POLE is contributing that excess phase shift inside the opamp).

Your opamp is also driving some load capacitance. Assume that is 10pF in series with Zout of the opamp. In this simulation, I included NO Cload. The opamp's output ESD diodes will provide 1pf or 2pF, if not more. Thus some cload is always there.

I would explore the inclusion of 0.1pF or 0.5pF across 10Meg Rfb. Some is inevitable; model it.

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  • \$\begingroup\$ thanks for the answer, I am picking up some of pieces. However, I do not understand the circuit maybe because I am not familiar with this circuit analysis program. \$\endgroup\$ – Navaro Mar 25 '19 at 22:17
  • \$\begingroup\$ However, I do not understand the circuit maybe because I am not familiar with this circuit analysis program. What I understand from your analysis is that reducing the value of the feedback resistor helps. But I am still not sure how to go about reducing the stray capacitance in the PCB? Can I easily do it with cutting the Polygone out at the input ? \$\endgroup\$ – Navaro Mar 25 '19 at 22:23
  • \$\begingroup\$ There are TWO opamps. Can you show the schematic. And move R2/R1 to be closer. You'll need to illustrate what you mean about the Polygon at the input. \$\endgroup\$ – analogsystemsrf Mar 26 '19 at 5:06

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