i am working on some CPLD-controlled SPI devices that will be daisy-chained together. I will be using 74VHCT126AFTTR tri-state buffers to disconnect the SPI and Slave Select lines on the device from the daisy-chaining cable.
I have now a few questions:
The 74VHCT126AFTTR buffer will be powered by a 5V power supply line that is shared with the devices. With this voltage supply, will this buffer a 3.3V logic level SPI signal to a 3.3V logic level on the buffer's output?
When the VCC line on the buffer is set to ground will this affect the input lines of the buffer significantly? Could this make a problem for the SPI communication of other devices on the same BUS?