I want to interface different boards with FPC/FFC or ribbon cable and I was wondering about the placement of the signals in the cable.

I plan to have a 39 signals FPC with :

  • 1 SPI bus (SCK, MOSI, MISO)
  • 4 GPIO for SPI Slave Select
  • 4 other GPIOs
  • 1 JTAG bus (TDO, TDIO, TMS, TCK)
  • 17 GND power wires
  • 7 +5V power wires

I plan to have that many GND wires in order to isolate signals from each other and in order to provide enough return path. The 7 +5V are here in order to provide enough current through the connector.

I placed a GND between almost every signal.

My question is about whether or not there is any issue with placing +5V power signal between SPI lines for example. Will it provide additional EMI or crostalk protection ? Or will it create more parasistic capacitance ?

PS : Similar question has already been discussed in previous topics and the conclusion is almost always the same : place GND between your digital signals. However I have not found any piece of information concerning other power signals such as +5V.

  • \$\begingroup\$ Generally this should be fine. Just how much current do you need though? What's the FFC rated for? \$\endgroup\$
    – Lundin
    Mar 25, 2019 at 10:41
  • \$\begingroup\$ You only indicate 34 signals. If you have 39 available then use every odd conductor as ground. Starting from one end use every even conductor as a signal and from the other end the even conductors are power. The spare 2 even conductors could be ground again to separate the two sections further. \$\endgroup\$
    – KalleMP
    Mar 25, 2019 at 17:41
  • \$\begingroup\$ @KalleMP There are 39 signals as SPI is a bus of 3 signals and JTAG one of 3 signals as well. All the power on one side of the ribbon won't create an "unbalanced" signal ? I have the feeling (I can't say why though) that it is not that good to put all the power lines on only one side of cable. \$\endgroup\$
    – tponc
    Mar 26, 2019 at 9:44
  • \$\begingroup\$ @J.K. Sorry, I just did a quick addition of your numbers, you had 4 for the GPIO but 1 for the SPI and I was sloppy in my sums. I would still use ground on every other wire and put the power all on one end. Sometimes the power is split between signal groups but there is little need unless you think one group would be more noisy than some other that is more sensitive. Alternate method is to take signal groups and power in blocks and divide ground between the blocks. Length of cable also matters, short cable less issues. JTAG placed next to group that is not used simultaneously etc.. \$\endgroup\$
    – KalleMP
    Mar 27, 2019 at 20:59

1 Answer 1


If your 7 wires of VDD are well-bypassed at the load end (using L+C low pass filters), then the AC behavior will be as quiet (or as trashy) as the Ground wires.

Fundamentally, use the bypass capacitors to form the fabled AC_short to between two wires: in this case, AC_short the VDD wires to the Ground wires.


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