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With a simple parallel plate design for a capacitor, does point of contact(to the external circuit) matter?

enter image description here

I imagine any point(a - e) would yield the same feature in storing/discharging charge. However, I'm curious if there is an optimal point of contact relative to to it's performance.

In addition, if I were to wrap these two plates parallel to one another to conserve some space, if I had the point of contact at (a) and wrapped the ends such that point(e) meets the point of contact(a) with a gap in-between would it function as normally? enter image description here

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  • \$\begingroup\$ Huh, a good question! I don't think it matters very much, as the plates are highly conductive, but it may have effects on high-frequency things. \$\endgroup\$
    – Hearth
    Mar 25, 2019 at 12:52
  • \$\begingroup\$ I agree, I'm curious about the high frequency aspect you mentioned, could you elaborate? \$\endgroup\$
    – mai
    Mar 29, 2019 at 13:41
  • \$\begingroup\$ Increased series inductance, mostly. \$\endgroup\$
    – Hearth
    Mar 29, 2019 at 13:54

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Performance specifications on Capacitors;

  • C [pF to F]
  • Tolerance of C [%]
  • Vmax [V]
  • leakage current @ Vmax [uA]
  • ripple current [Arms] some temp rise.
  • dissipation factor ( % of 120Hz power lost for rectifiers)
  • SRF (self resonant frequency due to inductance)

Joining "a" to "e" are in the same conductor plate and thus have the same E-Field so it is not a variable for capacitance design.

When the other plate is joined to itself we now have a coaxial capacitor. This is dependent on the gap and dielectric constant to yield some C value in picoFarads per meter. e.g. coax cable ~ 100 pF/m E fields between 2 points decay rapidly with gap will depend on this geometry of equal potential, namely by ;

  • 1/r³ from a point,
  • 1/r² from an edge
  • 1/r from a large area.

Getting to a "tiny centre point " now degrades the contact resistance and with a skinny wire adds inductance.

So this is counter-productive to "performance". Although the ideal conductor has the same voltage at every point, there is conductor resistance but it still does not affect a constant E field between the plates .

The Effective Series Resistance, ESR is limited by the area to dielectric total area contact. This conductor surface may be etched to increase the roughness and effective surface area to thus drop the ESR.

The contact point should be at least the entire edge.

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To minimize series inductance and resistance (particularly important when the plates are thin metalization) you normally want to connect to the entire edge of the plate.

To do that, the plates are wound so that they each overlap the dielectric a bit one side (either foil plates or the metalization on the film) and then each entire end of the roll is glomped together with something conductive (referred to as "schoopage" in the Wiki article linked below) to connect the plate to a lead wire or terminal.

The Wikipedia article illustrates stacked film caps and shows a complete uncoated film cap.

enter image description here

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"Performance" is usually defined in terms of ESR / ESL. In this regard, having contact points in the middle of the plates helps reducing ESR/ESL. So does having contacts points in mirror-symmetrical locations (rather than on opposite sides) and reducing the plates' perimeter.

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Integrated Circuit designers have this decision to make, for every capacitor they use. If the capacitor plates are POLYSILICON, the ohms-per-square are (perhaps) 50 ohms/square. This inherent resistance (10,000X higher than an 35micron thick piece of copper foil) makes the contact point-or-side and aspect_ratio become key for circuit SPEED and for the dampening.

When the designer places on-chip capacitors, to supply the 100 picosecond demands for charge as the logic system changes state, the inductance of metallization and of the bondwire+leadframe_package will interact with all the onchip parasitics and intentional (e.g. the polysilicon or even Metal_insulator_metal) capacitance and will resonate.

The designer of the silicon system has the responsibility to design, to dampen, the L+C energy storage network.

On a PCB, the designer has the same responsibility to design. Or they can just punt and hope.

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