Are there any caveats with tapping off the base of a BJT to drive a high-impedance load, such as a logic gate or op-amp? In the schematic below, I have an open-collector output from U1 sinking base current from transistor Q1 to operate a load. I would like to connect some downstream logic to the output of U1 for use elsewhere in the circuit.

The only issue I can see with this approach is ensuring that the saturation voltage of the open-collector output is low enough to register "logic low" with the downstream logic. As long as the base current of Q1 is relatively low, and U1 isn't sinking much current, I think this is attainable. (The actual thresholds will depend on the components used, of course.)

Is this practice okay, or would I be better off buffering the output to Q1 so all of the loads on U1 are high impedance? Or, is there some other design practice that's more appropriate here?

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  • \$\begingroup\$ You need to specify the value of '+V'. It has to be compatible with the logic family being used. \$\endgroup\$ – Kevin White Mar 25 at 21:19
  • \$\begingroup\$ @KevinWhite Good point; I left it generic for brevity. Let's say 5 V on both +V lines in the schematic. \$\endgroup\$ – higrafey Mar 25 at 21:32
  • \$\begingroup\$ No, but the current won't come from Q1's base anyway. If the current does come from Q1's base then your impedance is too low and the load will cause Q1 to turn on. \$\endgroup\$ – immibis Mar 26 at 1:27
  • \$\begingroup\$ @immibis That makes sense. I figured that the ~100 nA current for the logic would come from R1 when U1 is turned off. \$\endgroup\$ – higrafey Mar 26 at 2:05

Unless I really needed to save space, or was designing something that would get manufactured 100,000 at a time, I think I'd follow U1 with single-gate buffer, and drive the transistor (and the following logic) from that.

Your scheme would only work reliably if it picks the junction of R1 and R2 up above the positive threshold for the following logic -- which would be around 2.5V for TTL or HCT logic, but something like 3.5V for CMOS.

  • \$\begingroup\$ Thanks for the response. But, if the actual base of Q1 was tapped, wouldn't the logic signal alternate between +V and (+V minus Vbe), e.g. 5 V and 4.3 V? I'm not sure I understand how it could get to a logic low. \$\endgroup\$ – higrafey Mar 26 at 0:41
  • \$\begingroup\$ Thanks for the catch -- I looked at your PNP in common-collector and saw a common emitter NPN circuit. I've deleted the outright wrong part of my answer and replaced it with something more sensible. \$\endgroup\$ – TimWescott Mar 26 at 0:50
  • \$\begingroup\$ No worries--thanks for updating your answer! Regarding the single-gate buffer you mentioned, would that just be to avoid U1's open-collector output in this situation? What if the output were push-pull instead? \$\endgroup\$ – higrafey Mar 26 at 1:54
  • \$\begingroup\$ If U1 were a CMOS push-pull, then your circuit would be fine as-is. With TTL, you'd want to check -- they don't pull all the way up to VCC (as in, 74LS lists 2.5V guaranteed, 3.4V "typical"). If it's modern parts, it's CMOS. \$\endgroup\$ – TimWescott Mar 26 at 2:13
  • \$\begingroup\$ That's helpful to know. I suppose with either TTL or CMOS push-pull, I could drop R1 since it was only serving as a pull-up resistor on the open-collector output. \$\endgroup\$ – higrafey Mar 26 at 2:43

Every TTL family series has the identical input threshold of two Vbe drops or 1.35 to 1.4V at room temp but vary on logic low input current and output speed. The CMOS 74HCxx family was made almost the same at 1.5V as this was the Vgs(th) threshold voltage used in Nch 5V CMOS.

Input states are defined with margin as 0.8V max = "0" and 2V min="1". But this is for good immunity only as the PN and diode thresholds shift with temperature.

Your active load is more likely to draw much more current than the logic input. Therefore the chances of not meeting logic valid levels are very unlikely even with poor margins.

The only caveat is to use at least 5% of your collector current for the base current.

  • \$\begingroup\$ I'm thinking relatively low current here, so the load from Q1 would be maybe 10-20 mA with Ic/Ib around 10 for safe measures. Most of the logic chips I'm looking at are rated at 100 nA maximum input current with a typical value many magnitudes smaller. \$\endgroup\$ – higrafey Mar 26 at 0:47
  • \$\begingroup\$ So then all you need is 1-2 mA for Ib \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Mar 26 at 1:01
  • \$\begingroup\$ Right, not very much current at all for Q1 :-) \$\endgroup\$ – higrafey Mar 26 at 1:55
  • \$\begingroup\$ You certainly don’t need a buffer and perhaps not even Q1 if you invert in software or drive load on low side. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Mar 26 at 2:11
  • \$\begingroup\$ Ah yes, that's a good point if U1 can sink enough current. FWIW, I had a jellybean comparator in mind for U1 when I made the schematic. No software and not much current sinking ability :-/ \$\endgroup\$ – higrafey Mar 26 at 2:47

The way I have done this is put R1 across the base-emitter of Q1, it can be 1K or less. Now when U1 is off the output still pulls up to V+, but the other loads can draw a bit of current without turning on Q1 ( it turns off faster too.)

  • \$\begingroup\$ Oh okay, that's usually where I locate my pull-up/down resistors when I'm driving a BJT from a single output. In this situation, will you also move the TTL/CMOS line directly to the base of the transistor? (In other words, shift R2 to the left side of the junction point in the schematic above.) \$\endgroup\$ – higrafey Mar 27 at 1:58
  • \$\begingroup\$ No. Keep them connected to the output of U1. As far as they need to know they are connected to an open collector output with a pull up of R2. \$\endgroup\$ – EinarA Mar 27 at 23:34

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