I am using the following circuit in my design:

enter image description here

The desired behavior is the following: After #ON is turned low, the GATE output from U5 goes high (VIN voltage + around 6 V) and Q1 goes ON. After the #ON goes high, the GATE goes low (0 V) and Q1 transistor is off.

For some PCB pieces I have noticed the following behavior: De-asserting #ON (high state) doesn't make the Q1 go off (even though GATE voltage is 0 V). Q1 will go off only after sufficient amount of load is applied to VOUT (ie. I short VOUT to ground with a 10R resistor).

What could be the case in here?

  • \$\begingroup\$ For some PCB pieces ... other PCB's are working correctly? \$\endgroup\$ – Huisman Mar 26 at 9:31
  • \$\begingroup\$ Thats right. This is only for some of them. \$\endgroup\$ – Bremen Mar 26 at 9:33
  • \$\begingroup\$ What's the function of the LTC441? With CTL tied to IN, isn't the chip always shut down? \$\endgroup\$ – Huisman Mar 26 at 11:14
  • \$\begingroup\$ LTC4411 will become ON as soon, as one applies voltage to VOUT, that is higher than VIN. The VIN is tied to the battery. VOUT is tied to the load and/or to the charger. There is a situation in the software (very low battery level) in which Q1 is off for some time. In that case LTC4411 provides better charging path than Q1's body diode. \$\endgroup\$ – Bremen Mar 26 at 11:16
  • \$\begingroup\$ CTL (Pin 3): Controlled Shutdown Pin. Weak (3μA) Pull- Down. **Pull this pin high to shut down the IC**. Tie to GND to enable. \$\endgroup\$ – Huisman Mar 26 at 11:19

Q1 will leak current to the output and, if you look at its data sheet it might be as high as 10 uA (\$I_{DSS}\$). Additionally, U4 is also a contributor - if you read its data sheet, the leakage is also going to be several uA.

With insufficient load on the output to drag the output down when disabled, you will see a voltage. How much is dependent on your load.

You should also be aware that the absolute maximum input voltage for the LTC4411 is 6 volts and, you are likely pushing it beyond reasonable expectations with your 6 volt input supply.

  • \$\begingroup\$ I don't see 6V input in OP, Vin is not defined (yet). \$\endgroup\$ – Huisman Mar 26 at 9:30
  • \$\begingroup\$ Thank you for answer. Like @Huisman said, I dont supply 6V to VIN. For my design, its up to 4.5 V. The 6 V value is the gate voltage + VIN, which is in the Vgs range of Q1. The leakage currents you mention seem ok, because in total they are not even 1 mA. In my design, after the Q1 should be off, it is still supplying around 20 mA+, leds are blinking... I am wondering either it is not damaged. \$\endgroup\$ – Bremen Mar 26 at 9:33

Part of an answer:

enter image description here

If it [#ON Input] is driven high while the external MOSFET is turned on, GATE is pulled low with a weak pull-down current (40μA) to turn off the external MOSFET gradually.

The block diagram shows a 500k resistor. This resistor is connected to OUT, on which a 10uF capacitor is connected. It wonder if it will ever turn off as the 10uF is still charged by the open mosfet...

When applying 10R as load, you connect OUT to GND, and pull GATE below VGATE(TH) (see GATE HIGH COMPARATOR in block diagram), so the LTC4361 turns off.

Some examples shown in the datasheet of the LTC4361 show a Cout of 10uF, but ON is hardwired to GND!

  • \$\begingroup\$ Thank you for answer. But the point is, when the Q1 is still ON, the GATE voltage is 0 V \$\endgroup\$ – Bremen Mar 26 at 10:02
  • \$\begingroup\$ What voltage is on Vout when the GATE voltage is 0 V? \$\endgroup\$ – Huisman Mar 26 at 10:07
  • \$\begingroup\$ VIN - some voltage drop on the transistor and resistor, around 20 mV less \$\endgroup\$ – Bremen Mar 26 at 10:07
  • \$\begingroup\$ Excuse me for asking explicitly (as your remark can also be interpret as an analitical answer), but you measured Vgs of the SiR404DP? \$\endgroup\$ – Huisman Mar 26 at 10:13
  • \$\begingroup\$ 0 V is in reference to GND. In reference to VOUT its the -VOUT. So there is 0 V on the SiR404DP gate and it looks like its still conducting. \$\endgroup\$ – Bremen Mar 26 at 10:17

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