How add delays to everything in Verilog or SystemVerilog outside of .v or .sv file

Question

All delay documentation I've seen is pretty low level -- add a #5 or whatever and that particular assignment gets a delay. Use this in a module and instantiate, etc, etc. There are variations on this theme.

What I'm looking for is a way to assign a delay to each and every combinatorial equation or flip flop assignment, without cluttering up the .v file with # signs, and without having to instantiate tiny submodules to do simple things that can be done in a one-liner.

I want to be able to zoom in on a clock edge and see what comes right before and what comes right after, without everything being exactly at the same time, so I can understand the causality of an event. I'd like to be able to see combinatorial glitches. I'm also interested in asynchronous (clockless) circuits, so I'd like to see that stuff doesn't happen in zero time.

And I want to do this without having to go through a synthesis for some particular device. This doesn't need to be super precise, and I'm not looking for timing violations, eg setup and hold, or anything that is specific to a device or technology. I just want a generic way to tell the simulator to slow everything down by a little bit just to show that the delay is there. The delay can be arbitrarily small, but should be visible when I zoom in on the waveform.

Is there a way to add a generic delay to everything from the simulation tool?

Currently I'm using Icarus and Modelsim.

thanks

Answer 1

There is a delay_mode_unit that puts a #1 on every gate level primitive. Depending on the tool, it could be a command line option, or a compiler directive.

Any tool that dumps waveforms in a format other than VCD usually has a mode of dumping in what's called sequence time. This can show the order of signal changes within a single time slot. So there's no need to add arbitrary delays to move signals away from the clock edge.