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Wasn't sure how to headline this but here it is:

I'm debugging one of my coin cell ON/OFF switch. Circuit is as follows:

schematic

simulate this circuit – Schematic created using CircuitLab

Basically a high side switch for the coin cell that would power a uC.

I've tested the MOSFET named in the schematic and also FDY4000CZ - both have same issue:

Issue is, that I am seeing some premature logic level on "uC GPIO", which

1) when applying power causes Vcoin to be slightly attached.

2) When removing power, the MOSFET does some 'jumps'. In frequent cases, keeps oscillating on/off - very dangerous for the coin cell which it can be depleted.

  • So here I just remove all power (3.3V and Vcoin) after some runtime. uC GPIO is high. uC Vcc is slowly decreasing due to capacitance and uC is in sleep mode. At one point ~1.6V the MOSFET switch closes and cuts power - All is good.

  • But then uC GPIO does some wierd jump - this should not happen! One of my good units does not do that, same mosfet, same circuit...

Removing power CH1: yellow, uC GPIO

Nothing else attached for this measurement.

  • Here I am manually dropping Vcoin (from PSU) voltage until cutoff, but I can now see some oscillation - as if the uC tries to power itself from Vcoin, but cannot, as uC GPIO self-charges High and then goes Low again. - Nothing like this is programmed via FW.

(NB: uc GPIO does NOT go High in startup, so it doesn't seem to be startup FW issue. So there must be some leakage?) oscillation_on_off

  • CH1: yellow, uC GPIO
  • CH2: magneta, Gate of M2
  • CH3: purple, uC Vcc
  • (ignore CH4)

Closeup of the small peaks: enter image description here

All channels same as before. CH1: yellow, uC GPIO CH2: magneta, Gate of M2 CH3: purple, uC Vcc CH4: blue, is now Current from Vcoin.

I'm all out of ideas, why this happens, or how leakage can turn uC GPIO high for a moment...

(The pull-resistors could be too high aka weak, but I cannot go much lower (I've seen 500k kind of solve this oscillation issue) because I need to keep current consumption for this circuit very low. These 10M resistors allow me to draw ~5uA average in total - which would be ideal.)

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  • \$\begingroup\$ Why do you have two parallel diodes (D2 and D3)? \$\endgroup\$ – Hearth Mar 27 at 13:27
  • \$\begingroup\$ Does Vcoin mean we get free change (money ) after a power failure?? ;) If you shunt the drain-to-gate internal capacitance with a cap across Vgs , does it bypass the transient? \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Mar 27 at 13:42
  • \$\begingroup\$ @Hearth To allow better current capability from 3.3V directly. One diode can cause discrepancies among different batches, so two diodes average things out a bit. \$\endgroup\$ – crypton Mar 27 at 14:04
  • \$\begingroup\$ @SunnyskyguyEE75 Hah, unfortunately not, but I do get a free signal on GPIO during power failure, Just need to harvest it. Hmm, will give that a try. Will report soon. \$\endgroup\$ – crypton Mar 27 at 14:05
  • \$\begingroup\$ As long as you're aware that the current is not going to be evenly split between the diodes. \$\endgroup\$ – Hearth Mar 27 at 14:35
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My first impression was, that R1 and R2 are way oversized. 10M may be considered as an open circuit in some applications.

Try lowering those resistances and see if your oscillations persist.

If the oscillations stop you could raise the resistance again but bypass them with small value ceramic capacitors to provide a low impedance return for transients.

Designing low power systems is not easy and you will be tempted to use huge resistance values but they often cause problems like the one you describe.

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  • \$\begingroup\$ Yes, Mentioned that as well (probably got lost in my long ramble :D) "(The pull-resistors could be too high aka weak, but I cannot go much lower (I've seen 500k kind of solve this oscillation issue) because I need to keep current consumption for this circuit very low. These 10M resistors allow me to draw ~5uA average in total - which would be ideal.)" That was one of the first things I tried out, so I wanted to see if something else helps, before making that trade off. \$\endgroup\$ – crypton Mar 27 at 15:07
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No guarantees, but I've had good results in very roughly equivalent situations by adding a small amount of hysteresis to the control input.
In this case eg place a small resistor Rh in the source of FET M1 and return R2 to the top of Rh. How small "small" is is a matter of experiment or possibly of design - although in this case there are enough uncertainties that experiment is probably a good start.

When uCGPIO is low M1 is off and the top of Rh is at ground.
When uCGPIO goes high M1 turns on, the current in Rh produce a small positive voltage in Rh and the voltage on M1 gate increases.

This effect MAY be able to be increased slightly by placing a say 1 M resistor Rd between M1gate / R2 junction and uCGPIO. What this does is to provide a more formal voltage divider formed by [Rd] - [R2 - Rh].
Without Rd the increased voltage provided by Rh is attempting to "lift" uCGPIO which is low impedance. With Rd the voltage on the gate is able to be 'lifted' by voltage on Rh as Rd isolates the low impedance uC drive.

Hopefully :-).

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  • \$\begingroup\$ Thanks, Unfortunately I couldn't test this as my hardware doesn't allow me to have these edits. So I ended up with another 'solution'. \$\endgroup\$ – crypton Apr 13 at 19:54
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Decided to add my own answer, as I did slightly something else that was provided here by others.

I ended up using a different MOSFET, namely FDY4000CZ.

It showed more stable results even with my current high pull-up and -down resistors. So in a way @swles answer was the closest and also confirmed kind of my suspicions but wasn't a good solution with the original MOSFET as I needed to use ~500k resistors which increase low power consumption a lot.

But replacing the current MOSFET with another one, which has slightly higher threshold voltage, doesn't produce that long oscillations and dies off after a few peaks.

At least the circuit closes and won't discharge my coin cell. I can live with that :).

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