I am trying to find a logic level MOSFET for 3.3V operation.

In my case, I am trying to compare AOD510 & AO4402.

  • AOD510: \$\mathrm{R_{DS(on)}}\$ @ 4.5 \$\mathrm{V_{GS}}\$ = 0.004 ohm but has no rating for 2.5 \$\mathrm{V_{GS}}\$
  • AO4402: \$\mathrm{R_{DS(on)}}\$ @ 4.5 \$\mathrm{V_{GS}}\$ = 0.005 ohm & @ 2.5V = 0.007 ohm.

Will AOD510 have less \$\mathrm{R_{DS(on)}}\$ @ 2.5V then AO4402, since its \$\mathrm{R_{DS(on)}}\$ @ 4.5V is lower ?

I want to control a 12V, 2A load with a 3.3V microcontroller by using PWM & a MOSFET.

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    \$\begingroup\$ Likely no. The Rds as function of Vgs is "curvy", and the curves can be very different: having 0.004R at 4.5 V doesn't automatically imply that there will be any good ON state at 2.5V. Go with AO4402. \$\endgroup\$ – Ale..chenski Mar 27 at 19:14
  • \$\begingroup\$ Hard to say with certainty. What is the Vgs(th) for both FET's? Actually, I see that a good answer has been accepted. The graph is much better to look at than the Vgs(th). But Vgs(th) is a good thing to look at if there is no graph. \$\endgroup\$ – mkeith Mar 30 at 5:45

Will AOD510 have less RDS(on) @ 2.5V then AO4402, since its RDS(on) @ 4.5V is lower ?

No. At 2.5V it is not specified to be "on". You can check the Rdson vs Vgs graphs:


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At 3.3V you can't really be sure that AOD510 is on. At 3.3V Rdson of AO4402 should be in the ballpark of 5~7mR.

At steady state on Power dissipation should be less than 2Aˆ2 * 0.010R, so quite ok. If you are using PWM the losses are worse because you spend more time on the linear state, but as long as you dont use some ridiculously high gate resistor you should be fine.

  • \$\begingroup\$ Also, do I need to look into the Vds & Id graph for my purpose or is the value of Rds enough to be a deciding factor ? I am using PWM for controlling the load. \$\endgroup\$ – Electric_90 Mar 27 at 16:48
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    \$\begingroup\$ Vds will be basically a function of Ids * Rdson, so as long as you turn it on fast it should be ok. The labeling on the AO4402 datasheet is missing, but if you look at the AOD510 datasheet it just shows that at higher Vgs, Vds will increase less when current increases. \$\endgroup\$ – Wesley Lee Mar 27 at 16:56
  • \$\begingroup\$ So at the very basic level, I should just use Rds value for comparing the FETs for my application ? \$\endgroup\$ – Electric_90 Mar 27 at 17:03
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    \$\begingroup\$ And gate charge/capacitance, that with the current drive/series resistor of your MCU will make an RC filter that will keep the FET on linear region longer. And Vds/Vgs that are high enough for the voltages involved plus some margin (there might be some ringing depending on what/how hard you are driving it). For something like 12V and manageable current (such as 2A) I usually like to get parts rated for 35V, so if I ever need to use something that is 24V I have the option. And dont forget the flyback diode. \$\endgroup\$ – Wesley Lee Mar 27 at 17:12
  • \$\begingroup\$ If you are using PWM then life gets a lot more complicated. Basically, a microprocessor pin is wimpy. To do PWM, you need to turn the FET on and off significantly faster than your PWM to minimize switching losses. In general, I wouldn't PWM straight from a microprocessor pin unless the task were either human speed (10Hz or less), or I had run the numbers with the particular microprocessor, transistor, and PWM speed. \$\endgroup\$ – TimWescott Mar 27 at 18:53

The other posters have provided good answers, but one thing I see with beginners is that they focus entirely on Rds, and completely ignore gate capacitance. Since MOSFETs are made of many little fets in parallel, halving Rds means doubling Cdg and doubling switching losses. You want to strike a balance between Rds loss and switching losses so they are about equal. A 2A load does not require this low a Rds and you will be better off with something around 50 to 100 miliohm and proportionately lower Cdg.

  • \$\begingroup\$ This is so right, Coss*Rdson=T is an important figure of merit. when choosing optimal FET for Pd loss at some PWM rate. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Mar 30 at 4:01
  • \$\begingroup\$ Wouldn't Cgs also double? As the FET gets wider, the gate-bulk capacitance will increase, which is effectively the gate-source capacitance because bulk and source is shorted together? \$\endgroup\$ – Linkyyy Mar 30 at 15:15
  • \$\begingroup\$ Yes it will, but Cgs doesn't play a major role in switching losses. It primarily adds a delay before the FET starts to switch. But I am mostly ignoring the actual semiconductor physics and just considering Cgd a lumped value of all negative feedback capacitances. The goal is an intuitive sense of how different fets will behave than a precise definition. \$\endgroup\$ – EinarA Mar 31 at 3:07

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