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I am trying to understand why the paths with -ve slack in Slow_900mV_0C model do not show up in Slow_900mV_100C model. I am using Arria 10 GX.

I would think the process part of the model is likely the same in the two timing models, as such I would expect the circuit to run slower at higher temp and same voltage. Then why do those paths that have negative setup slack in Slow_900mV_0C model do not appear when I run the STA at Slow_900mV_100C corner?

Thank you. Best regards,

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  • \$\begingroup\$ Show where it appears and , where you expect it. This was also called a 4 corner Schmoo test at one time. Max speed is cold at high voltage and min speed is hot at low voltage. for CMOS, but not TTL \$\endgroup\$ – Sunnyskyguy EE75 Mar 27 at 20:37

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