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In the book CODE, there is a chapter on binary subtraction circuit.

First, it tells us how to subtract two binary numbers. The steps are (the example is for 8 bit numbers)

  1. Subtract the subtrahend from 11111111 (ones complement)
  2. Add the ones complement of the subtrahend to the minuend
  3. Add 1 to the result
  4. Subtract 10000000

And you get the result.

The circuit is illustrated: Circuit

The control box is: Control box

The circuit accomplishes step 1 through the ones complement box. It accomplishes step 2 through the 8 bit adder. It accomplishes step 3 through the first CIN, where its value is 1 if we're using SUB mode, and 0 if we're doing addition.

I don't get where step 4 is, how does this circuit produce the final correct result? Isn't it only doing the first 3 steps?

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  • \$\begingroup\$ "Subtract the subtrahend from 11111111 (ones complement)" that's not a ones complement. You get that by inverting every bit. \$\endgroup\$ – Finbarr Mar 28 at 10:04
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    \$\begingroup\$ @Finbarr How are you going to represent an inverter in maths notation, away from the world of circuits? Subtracting it from 11111111 is one's complement, try it. \$\endgroup\$ – Ammir Barakat Mar 28 at 10:41
  • \$\begingroup\$ True, but it's a nonsense to say that the first step in subtracting two binary numbers is... to subtract two binary numbers. \$\endgroup\$ – Finbarr Mar 28 at 20:03
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Your subtraction circuit is not a two's complement subtraction but a simple unsigned integer subtraction circuit, without borrow. I mention this because there is a separate meaning for underflow/overflow when two-complement is involved. (I suppose this will be a later section you read?)

For zero and positive-only values (unsigned values) the subtraction operation is easily handled by inverting all of the bits of the subtrahend and adding 1. For addition (without carry), the carry in (CI) is set to zero. (I'm assuming that the ADD instruction's decoded value for the SUB wire is "0".) Then the addition proceeds. However, for subtraction, providing the "1" bit at the CI input provides that +1 addition that's needed.

With addition, the carry out is just the carry out. But with subtraction handled in the above way, the carry out has a different meaning because the subtraction was actually being carried out using addition (it's an adder, after all) with adjustments made to the subtrahend to make it work out. So the carry out being a "1" actually now means the subtraction completed without needing to borrow from the next higher word. That last XOR on the left, under your edition of subtraction, inverts that back to a "0" to show that there was no "borrow" needed. In this case, this means that if the carry status result after the operation is "0" there was no overflow for either ADD or SUB instruction operations.

This design works after a fashion, but it is less common to find in practice. Instead, the XOR on the left isn't present at all. In this case, a carry status=1 means different things for ADD and SUB. For ADD, it may mean the need to pass along that carry to a higher order word in a subsequent addition operation. For SUB, it means there was no borrow from the higher order word of the minuend. Similarly, a carry status=0 means there's no carry into a higher order word for ADD, but instead means there is a borrow from the higher order word of the minuend for SUB.

Typical designs find it easier to simply latch the carry-out as the carry status without the XOR. The reason for this is pretty simple. If the CI is "1" for a SUB instruction, then the subtract occurs without borrow. But if the CI is "0" for a SUB instruction, then the subtract occurs with borrow taking place. Using your indicated method, this gets a little more complex and adds logic prior to CI (as well as to CO.) The added logic of which is really unnecessary.

There's another advantage in handling it the way I've just described and not the way you've illustrated. A single SUB instruction is all that is required, instead of two SUB instructions (subtract and subtract with borrow.) A multi-word subtraction would start with setting the carry status=1 and then performing SUB. The SUB instruction would place the carry status value at CI and perform its operation. The CO output would be latched as the next carry status value. A subsequent, higher-order word subtract (if desired) would simply perform a following SUB of the higher-order words. The carry status would already be correct for placing at CI without added gates to make things work right. Saving instruction space leaves open room for other important instructions and does this without any real cost (except the need to start a multi-word subtraction by setting the carry to "1".)

That said, there are MCUs (older, in my recollection) which handle it the way you've described.

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Subtracting 100000000 is the same as adding 011111111 + 1, so only the carry bit is affected. That's what the ex-or gate is doing.

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You have 2 errors. One's complement is (as already commented) inversion bit by bit. Actually the result is the same, but the linked circuit makes inversion, it doesn't apply arithmetic subtraction.

You have written wrong step 4. It should be "omit bit 8" from the result, use it inverted as underflow indicator. Bit 8 will normally be 1, but the result contains only bits 0...7. If bit 8 happens to become zero, there's underflow, the available number range is exceeded. Formally inversion of bit 8 can be written as "subtract 100000000".

To be exact, bit 8 isn't ignored, it can be used systematically to implement larger number range in 8 bit chunks.

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  • \$\begingroup\$ Nothing I wrote is wrong. It's all from the book CODE. And it all makes sense mathematically (adding and subtracting the same number to an operation doesn't change it). As I explained in my post, the maths steps are translated to circuits through various objects. I don't understand the translation of the last step. \$\endgroup\$ – Ammir Barakat Mar 28 at 10:51
  • \$\begingroup\$ @AmmirBarakat I bet step 4 should be written "subtract 100000000", not "subtract 10000000". My suggestion is implemented having only 8 bit result + inverted carry bit as overflow indicator. Your version is not implemented in the circuit. \$\endgroup\$ – user287001 Mar 28 at 23:55

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