I read that PLL are used in CPU to generate the clock, but I can't understand why.

I don't really have any guess of why this is.

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    \$\begingroup\$ I would shut this question down as "too broad". It is like asking "why are there CMOS gates instead of transistors in a CPU"... \$\endgroup\$ Commented Mar 28, 2019 at 22:20
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    \$\begingroup\$ It is probably too broad but I got very relevant answers that will hopefully help other people. \$\endgroup\$ Commented Mar 28, 2019 at 22:30
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    \$\begingroup\$ Why close this? It invites tutorial style questions covering the subject in general which will be of ongoing interest to others. \$\endgroup\$
    – Russell McMahon
    Commented Mar 31, 2019 at 4:22

5 Answers 5


There are several reasons for this. A phase locked loop, or PLL, is a circuit that is used to generate a stable frequency that has a specific mathematical relationship to some reference frequency. Specifically, it is a circuit that is used to control some sort of electrically tunable oscillator (usually a voltage controlled oscillator, or VCO) so that its output is locked into a specific relationship with a reference frequency that is supplied by some sort of stable reference (usually a crystal, crystal oscillator, or silicon MEMS oscillator).

A PLL works by dividing down the output of the VCO and the reference input with frequency dividers, then comparing the frequency and phase of these divided outputs and adjusting the VCO control voltage until the frequency and phase align.

It is possible for a PLL to generate a much higher frequency than the reference frequency - for example, a 100 MHz reference can be multiplied up to several GHz. If the PLL is integrated on the same chip where the high frequency output is used, this can save power and reduce EMI by lowering the frequency that is sent through the circuit board traces. It also makes the board layout simpler.

Since the relationship is determined with simple frequency dividers and it is quite simple to build programmable dividers, it is very easy to change the output frequency of a PLL by simply changing the divider settings. This can enable power savings using a technique called dynamic frequency scaling, where the frequency is adjusted based on the required processor performance to reduce power consumption. It also enables software-based configuration of the frequency, which makes the design of the system much more flexible as software can decide what settings to use at boot time based on detected hardware (for example, looking at CPU socket pin strapping or reading out SPD EEPROM contents on RAM modules during boot).

In a modern CPU, there are going to be multiple PLLs present for providing the clocks for various components. Modern CPUs have a high level of integration and so components that used to be located on separate chips are increasingly integrated onto one die - there is a lot more than a single processing core and a front side bus on a modern CPU. The processing cores themselves will run on one or more clocks that are supplied by one or more PLLs so the core clocks can be adjusted easily, and possibly can be adjusted independently. The PCI express interface will also require PLLs, likely multiple PLLs to support operation at different link rates. Serial ATA connections likewise operate at a different speed and hence will have their own PLLs. Same goes for QPI, hyper transport, USB 3, HDMI, display port, etc. The memory interface likely requires a different PLL to generate the specific clock frequency that the installed memory requires. All of these PLLs would use the same (relatively) low frequency reference oscillator on the motherboard.

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    \$\begingroup\$ A critical issue you've missed is the difficulty of making a quartz oscillator above a few hundred MHz. Using a PLL allows the base frequency to be generated with high stability, then upconverted to GHz frequencies with little loss of stability. \$\endgroup\$ Commented Mar 29, 2019 at 2:26
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    \$\begingroup\$ @WhatRoughBeast: I don't think that's actually nearly as big an issue as moving the full frequency clock across the board without adding jitter and degrading edges. No one works on solving the problem of higher frequency oscillators, because no one would buy the solution. \$\endgroup\$
    – Ben Voigt
    Commented Mar 29, 2019 at 17:21

Been there, done that.

Apart from other reasons mentioned here is a different one:
The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ones use for Ethernet fall in that category. So you often end up having to use a 25MHz crystal.

At the same time marketing want powerful processors. Thus the processor (Let's call it a LEG++) should be able to run at 1 or 2 GHz.
The only way to do that is to use a PLL.

Or the processor can run at max 64MHz, but they want to have a USB interface which requires a 48MHz Clock. Again PLL to the rescue.

++LEG is not a registered trademark. (At least as far as I know)

  • \$\begingroup\$ LEG have just released a quintuple Toe version of their famous FOOT processor. \$\endgroup\$ Commented Mar 29, 2019 at 14:16
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    \$\begingroup\$ @TomCarpenter: I worked for a company in Cambridge which had a text with the title "ARM shows Intel the Finger" on the wall. It was a beautiful 1'st of April article where they specified a one bit processor called "The Finger". Never found a copy! \$\endgroup\$
    – Oldfart
    Commented Mar 29, 2019 at 14:26

PLLs can be used to multiply and divide frequencies. CPUs that have PLLs to generate their clocks are highly reconfigurable. The clock speed can be varied relative to the external reference clock over a wide range, and it's the PLL that makes this possible.

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    \$\begingroup\$ Also it is not possible to get xtals to oscillate much beyond 100MHZ, so the ref oscillator needs to be multiplied many times to get 1 GHZ to 4 GHZ core frequencies. Core frequency is usually a integer multiple of the ref xtal. \$\endgroup\$
    – user105652
    Commented Mar 28, 2019 at 18:56
  • \$\begingroup\$ Well, it is more generally going to be an integer ratio of the reference frequency, as the PLL can divide both the VCO output as well as the reference frequency. \$\endgroup\$ Commented Mar 28, 2019 at 23:06

PLLs are used primarily to generate one or more faster or slower clocks from a reference clock.

You might have say a fixed 100MHz crystal, but then want to run your CPU at 2GHz, so a PLL is required to increase the frequency (a 2GHz clock crystal isn't feasible).

Additional you may want to be able to change your CPU frequency on the fly (e.g. a turbo clock). In which case you could have a reconfigurable PLL.

Furthermore you may need a different memory or peripheral clock to your CPU clock. Again a PLL and divider can be used to generate this from a single reference.


3 main reasons;

1) power savings for mobiles and extend CPU life keeping cool.
2) signal integrity is improved using xx multiplier for front side bus due to short wavelength, lower capacitance
3) flexible CPU speeds are possible with throttle on Clock multiplier and Vdd to allow burst CPU power and cool down.

Signal routing of 100MHz FSB is easy, > 1GHz is hard and your CPU is much higher, driver current increases with f and standing wave reflections distort square waves. While reducing CPU clock saves power and reduces temp.


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