# Timing two parallel lines on FPGA [Beginner]

So let's suppose I want to do certain action based on certain signal. I have signal "nx"; if it's 1, I want to "NOT" an X input(16bit) and if it isn't, I want the X unchanged.

My idea was to do both and fanout it into MUX and decide which output to use based on the "nx" bit. But I'm not so sure if it would work in real hardware (or even FPGA for that matter), because the lane that doesn't change anything is gonna be carried out faster than the one with "NOT" gates in it.

Is my understanding correct ? And if so, is it problem even on FPGA (do those operations really "eat" clock cycles) ? And if so, how would you go about it to solve this simple problem ?

• Things on an FPGA don't "eat clock cycles" in the way you're thinking. Everything you put into a process will all take take one clock cycle. If the synthesizer cannot route that process and meet your clock constraints, it will tell you and you will either have to modify the design, or run with a slower clock. This "manualness" lets you time everything that happens in an FPGA down to the clock cycle, unlike a processor where you don't have full control of how many clock cycles something might take. – DKNguyen Mar 28 at 18:35
• So one path can be faster than the other. Every combinatorial circuit has different length paths. But as long as you give it enough time to propagate you will have the correct result. This is why we have a notion of a "critical path". Combinatorial circuits do not have clocks. – Eugene Sh. Mar 28 at 18:35
• "Combinatorial circuits do not have clocks", that sums it all nicely. Thanks you both so much for the awesome answers!!! I'll take a look at the warnings, if any emerge then – ShinobiUltra Mar 28 at 18:50

The function you're describing would be implemented as a single 2-LUT for each bit of X (with the function Xout[i] = X[i] ^ NX), not as two separate combinational paths. The propagation time of the LUT is independent of the logic which it was synthesized from.