I'm trying to modify an existing init sequence (low level init of SDRAM) to accommodate a change in hardware configuration: an existing SDRAM on my iMX31 was replaced with a different size, otherwise same type/manufacturer/layout/pins/timings .. according to specs.

Brief setup scenario and error behavior: I managed to get the board booting (the sequence is as such: execute bootloader from NAND, copy 'step2 bootloader' to RAM, execute 'step2 bootloader' from RAM). But I seem to have some settings wrong, since execution from RAM (after jump to to step2) fails consistently.

I did a large amount of in-depth test to identify wrong parameters, my results are these: - single byte/word reads/writes work when executed from NAND or JTAG - block-wise/burst writes seem to work when executed from NAND (JTAG also) The interesting thing: - after block-wise writes, I need multiple reads on any SDRAM address to read a correct byte/word(!) - if I modify my column settings to ONLY use the higher (+1) amount of columns for "load mode" but not for precharge/refresh, then it works, but inconsistently (to my theory it works reliably for the lower address range, where the missing column doesn't matter).

To get an idea of my config: the settings from RAM are almost identical to the ones in this question. This is not surprising, since they are supplied by Freescale, beside RAM timings: On Freescale iMX31, how can I translate SDRAM address to CPU address? My original setting is identical (also 64MB SDRAM as in link), my new RAM is 128MB. All reference boards are supplied with either 64MB or 128MB, thus both values are supported by iMX31 and derivates.

The change I have to make (attention:assumption!) is only in the COLUMN configuration (it's one more column) of the RAM. The RAM is double in size, but otherwise the spec claims exact same timings etc.. Since it has only one more column (see link above, my precharge, refresh and load mode registers change from 0x92100000 to 0x92200000 for the new RAM - for example) nothing else is changed.

Question 1: Does my assumption make sense, that if all timings and physical chip characteristics (affecting drive strength, timing and power consumptions) are similar, that a change of the column count might be "local" (not affecting other settings)? Interesting enough, I compared my settings with many other ones available online (U-Boot, Red-Boot with 128MB) and beside board specific settings, such as drive strength, I don't see differences.

Question 2: My error behavior above (writes work, reads only partial) is probably unique to a certain invalid setting of the RAM. Is anyone able to give me an advise which setting to have a closer look at? Also it might be possible to set 'safe' parameters so that even with diminished performance, the system would allow me to narrow down the culprit.

  • \$\begingroup\$ Are you reasonably certain the problem is not related to hardware design (bad ICs, layout errors, poor signal integrity, insufficient power...)? \$\endgroup\$
    – jbarlow
    Dec 6, 2012 at 7:11

1 Answer 1


For 2, start with settings from an iMX31 demo board. Then modify them as required for your part (speed and size mainly). In particular you probably have the wrong number of wait states on read.


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