This is my first PCB design and I'm struggling with proper copper pour usage.

I would like to copper pour VCC and GND.

From what I understand, a copper pour will net multilayer plated through holes automatically. When properly done, it is helpful for most boards. (I just love the fact that I can connect VCC and GND without traces)

Please help me understand the best placement of VCC and GND copper pours in 4-layer PCB.

I think, Top (GND), layer2 (VCC), layer3 (GND), layer4 (GND)?

Added Info: All components on top layer, 5MHz using SPI w/ Mode0, board is large (35cm X 35cm), 4 layers.

  • \$\begingroup\$ What's the function of your board? What kinds of frequencies (and raise times) do you have on your board? \$\endgroup\$ Commented Mar 28, 2019 at 22:44
  • \$\begingroup\$ Will you have components on both sides, or only on the top? And, again, what are your fastest signal frequencies or rise-times? Please edit your question to include this information. \$\endgroup\$
    – The Photon
    Commented Mar 28, 2019 at 22:57
  • \$\begingroup\$ Raw boards are already covered in copper, then holes and routing are done, then vias, etching, platings, then mask and silkscreens. You are determining how much copper to remove due to many factors such as capacitance, inductance, flight time, slew rates, ground bounce, dynamic currents, Vdrop, RF echos, etc. \$\endgroup\$
    – user105652
    Commented Mar 28, 2019 at 23:25
  • \$\begingroup\$ Info: All components on top layer, 5MHz using SPI w/ Mode0, board is large (35cm X 35cm), 4 layers, I just want to be lazy and use copper pour for VCC and GND connections - I also don't want to do it improperly and mess up the board. Thanks \$\endgroup\$
    – Sargent0
    Commented Mar 29, 2019 at 0:32
  • \$\begingroup\$ Are the signals possessing 2nanosecond rise times? or 20 nanosecond rise times? \$\endgroup\$ Commented Mar 29, 2019 at 2:50

1 Answer 1


5MHz is not an issue. Just use the two inner layers for VCC and GND. You will still need bypass capacitors, of course, as close to the VCC pad as you can put them. A via to GND should be fine.

When I do four-layer boards, I either do not bother with copper pours on the outer layers, or I just do GND pours. This is just cargo-culting, I do not have a good argument for doing it either way, except that it looks better with a copper pour even under the solder mask :)

I do not normally do very high speed stuff requiring transmission-line impedance calculations or worrying about equal track lengths and so on, so don't take my word as received wisdom.

It would be great if one of the more knowledgeable members of the board could point us to a good reference for what constitutes best practices for high-speed design (for various values of "high speed") in the context of amateur work.

  • 2
    \$\begingroup\$ Produces less waste chemicals and etches faster if you leave pours on the outer layers rather than etching it all away. Just don't leave the pours floating. \$\endgroup\$
    – DKNguyen
    Commented Mar 29, 2019 at 0:57
  • \$\begingroup\$ LOL... On the other hand, they get to recycle the copper and also not waste an extra drop of jet fuel when shipping it :) \$\endgroup\$
    – JayEye
    Commented Mar 29, 2019 at 0:58
  • 1
    \$\begingroup\$ The more dominant the ground plane, assuming no clash with RF traces, the lower ground bounce. Diamond cut pattern normally used for GHZ frequencies. Heavy Vcc traces cut Vdrop, but allow less wiggle room for other parts. \$\endgroup\$
    – user105652
    Commented Mar 29, 2019 at 1:00
  • \$\begingroup\$ Also good point about not leaving them floating. Always use the DRC feature to look for disconnects. You would have already specified that your (outer) pours are ground, so if any islands form, you should get a warning that they are disconnected. A couple of vias (preferably blind vias if your fab supports them) should solve that problem. \$\endgroup\$
    – JayEye
    Commented Mar 29, 2019 at 1:02
  • \$\begingroup\$ How do you prevent floating? Can I accidentally short the VCC and GND layers? \$\endgroup\$
    – Sargent0
    Commented Mar 29, 2019 at 4:41

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