# Phase Noise In a Voltage Controlled Oscillator

I am particularly new in VCO design. I am required to build a negative gm oscillator with f=7.4 GHz with a tuning range of 300 MHz. The phase noise should be -110 dBc/Hz at 1 MHz offset.

I sized the varactors in the circuit to have Cmax=550 fF, Cmin=330 fF with a tuning voltage of 1 V. The Tank capacitance was calculated to be around 2.2 pF/side with inductors of 190 pH, Q ~15. The differential transistors are sized 0.32/0.06 um process with bias current of 2 mA, 1 mA differential current. With many iterations with respect to changing the design variables I still cannot achieve the theoretical -30/-20 dB slope that is seen in typical phase noise responses in a VCO. All simulations are conducted in Cadence - Spectre If there are any tips on how to fix this it would be much appreciated.

I've designed RF VCOs before, the last one was at 30 GHz ;-)

My first step is always to check the theoretical properties of the tank, determine what the phasenoise would be assuming that the active part (the transistors) behave as ideal switches and do not add noise.

For this I have a Matlab script (actually I use Octave, a freeware Matlab clone). I wrote this script myself, feel free to use and share :-) I have included the script for your convenience:

################################################################################
# VCO_ideal_PhaseNoise.m
################################################################################
echo off; clear all; format short eng;
#Determine resonance frequency, C and L of resonator:
Fc = 0;
L  = 2*190E-12;
C  = 2.2E-12 / 2;

if (L*C != 0)
Fc = 1 / (2 * pi * sqrt(L * C));
endif
if (Fc*L != 0)
C = 1 / (4 * L * (pi * Fc)^2);
endif
if (Fc*C != 0)
L = 1 / (4 * C * (pi * Fc)^2);
endif
#Print the resonator's parameters:
Fc
L
C
################################################################################
# Active part of the VCO:
Itail = 4E-3;
Vout_diff = 0.5;

Rp = (pi * Vout_diff) / (2 * Itail);

Itail = (pi * Vout_diff) / (2 * Rp);

#Print the VCO's parameters:
Itail
Vout_diff
Rp
################################################################################
# Quality -3 dB Bandwidth and parallel resistance Rp:
################################################################################
Q = 15;
BW = 0;
Rp = Rp;
#Impedance at resonance:
Zres = 2 * pi * Fc * L;
if (Fc * BW != 0)
Q = Fc/BW;
endif
if (Rp * Zres != 0)
Q = Rp/Zres;
endif
if (Fc * Q != 0)
BW = Fc/Q;
endif
if (Q * Zres != 0)
Rp = Q * Zres;
endif
################################################################################
#Print more of the resonator's parameters:
Q
BW
Rp
################################################################################
#When used in a VCO this will give a CNR (active part assumed noiseless) of:
deltaF = 1E6;
Kboltz = 1.38E-23;
Temp = 300;

v = ((Fc + deltaF) / Fc ) - (Fc / (Fc + deltaF))
CNR = 10 * log10((2 * Kboltz * Temp * Rp) / (((Vout_diff/sqrt(2) * v * Q)^2)));

printf("At deltaF = %e Hz:\n", deltaF)
printf("CNR = %.2f dBc\n", CNR)


The code under "#Determine resonance frequency, C and L of resonator:" is a "solver" which determines Fc, L and C. Only two of those need to be filled in. I set Fc = 0 and then the script automatically finds out it needs to calculate Fc from L and C.

There's a similar solver for R (parallel resistance), Q and BW.

I made an assumption for the voltage across the tank: Vout_diff = 0.5 You can correct that of course.

When run it outputs:

Fc =     7.7845e+009
L =   380.0000e-012
C =     1.1000e-012
Itail =     4.0000e-003
Vout_diff =   500.0000e-003
Rp =   196.3495e+000
Q =    10.5641e+000
BW =   736.8813e+006
Rp =   196.3495e+000
v =   256.9036e-006
At deltaF = 1.000000e+06 Hz:
CNR = -117.53 dBc


Conclusion: You should be able to achieve -117 dBc at 1 MHz with this tank, there is only 7 dB margin to the required 110 dBc but that could be enough.

My next step would be to only add the cross-coupled NMOS pair (M0 and M4) and their biasing. So just copy your schematic and remove everything that is at the right of V1 (the buffer stage). You might want to add an ideal capacitor to emulate the load of that buffer stage.

Simulate again but only transient or PSS (shooting method), no phasenoise yet! We first need to determine if the cross-coupled NMOS pair is switching properly. Of course you can't get "hard" switching at 7 GHz but the noise added by these NMOS is worst when they're transitioning between on and off.

You might need to increase the W/L of the cross-coupled NMOS pair. That adds capacitance to the tank so remove some capacitance from the tank. Pro tip: you can add a capacitor with a negative value and that will remove some capacitance from the tank! So you can also sweep a capacitor from -1 pF to + 1 pF to find what capacitance you need to get back at the right frequency.

• How is CNR computed? Mar 29, 2019 at 14:24
• @analogsystemsrf Look at the code, almost at the bottom. The formula calculates the ratio between the signal (Vout_diff) and the noise at the carrier + offeset frequency. You can find this formula in many textbooks and lectures. I have confirmed the behavior of the script with an ideal RLC oscillator in Cadence Spectre. It matches that exactly. Mar 29, 2019 at 16:25