# Creating D-latch using Nand gates in Logisim?

I have designed a D-latch using NAND gates. The problem is when I convert it into a subcircuit the output is False no matter what my second input(clock input)is? It only works if I put the default clock input?

My D-latch

Subcircuit of the D-latch

As u can see the clock input wire is blue means it doesn't affect the output at all?

You should get and use Neemann's Digital, instead. It's much better and is currently maintained, as well. Logisim is pretty much a dead project and has been for some years, now.

## Logisim Behavior During Creation of a D-Latch

In Logisim, your RS stage at the end of your D-latch has outputs tied back to inputs used to determine that output. When you first drew out the four NAND gates and wired them up, you should have seen two red wires prior to simulation (using the pointed finger cursor.) However, once you poked the CLK line a few times, all that should have cleared up and your circuit will look fine, afterwards. As shown here:

## Logisim Behavior Using Your D-Latch

However, when you save it and then load/use it as a new circuit element on a new schematic, the output will show a tiny red dot indicating that the D-latch has those two red wires back, again. But again, if you wire up the part and provide it with some input and toggle the CLK line, that issue will again clear up and be fine. As shown here:

You can see that even in simulation, nothing gets fixed until you change the CLK input. But once that's done, the lines clear up and it looks as you'd expected.

## So Use Digital

Doing this in large circuits is what really makes using Logisim a bit of a pain, given that Digital exists (it doesn't have this particular problem and it solves many others.)

Digital can also generate verilog:

module \D-LATCH  (
input D,
input CLK,
output Q
);
wire Q_temp;
assign Q_temp = ~ (~ (D & CLK) & ~ (Q_temp & ~ (~ (D & CLK) & CLK)));
assign Q = Q_temp;
endmodule


and VHDL:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity main is
port (
D: in std_logic;
CLK: in std_logic;
Q: out std_logic);
end main;

architecture Behavioral of main is
signal Q_temp: std_logic;
begin
Q_temp <= NOT (NOT (D AND CLK) AND NOT (Q_temp AND NOT (NOT (D AND CLK) AND CLK)));
Q <= Q_temp;
end Behavioral;


and supports the BASYS3 board and the Mimas and Mimas V2 boards.

You can also use Digital with VHDL or verilog code, too, using the open-source VHDL simulator ghdl and the open-source Verilog simulator Icarus Verilog.

As u can see the clock input wire is blue means it doesn't affect the output at all?

No, that just means the net is undriven. Your "CLK" input pin isn't lined up correctly with the wire.