# What is the effect on propagation delay when we have a CMOS circuit with multiple transistors connected in series?

How does the fact that in a series connection of two or more transistors only one is connected directly to gnd (in case of nmos transistors) or vdd (in case of pmos transistors) effect the change of the output?

I am trying to simulate a CMOS OR circuit and need to make the propagation delay of the falling and rising edge equal and am getting different results even though the input signals are not different other than their names. So i guess it has something to do with the fact that one of the input signals is connected to the transistor connected directly to vdd or gnd and the other ones connected in series are not.

Could someone explain why that is?

As you observe, when transistors are in series then only one transistor has its source connected to ground. The sources of the other transistors will be at a higher voltage until the transistors below them all start conducting and bringing the source voltage lower, which means that $$\V_{GS}\$$ will also be lower for the series transistors until the transistors closer to ground have conducted current.
Finally, even when all of the transistors in series are conducting you will have the series combination of their $$\R_{DS}\$$ values. Generally the transistors in series are made a little wider so that their series resistance is not so large.