1
\$\begingroup\$

How does the fact that in a series connection of two or more transistors only one is connected directly to gnd (in case of nmos transistors) or vdd (in case of pmos transistors) effect the change of the output?

I am trying to simulate a CMOS OR circuit and need to make the propagation delay of the falling and rising edge equal and am getting different results even though the input signals are not different other than their names. So i guess it has something to do with the fact that one of the input signals is connected to the transistor connected directly to vdd or gnd and the other ones connected in series are not.

Could someone explain why that is?

\$\endgroup\$
1
\$\begingroup\$

It is a combination of several effects. To make the discussion easier to follow, let's just talk about NMOS transistors.

As you observe, when transistors are in series then only one transistor has its source connected to ground. The sources of the other transistors will be at a higher voltage until the transistors below them all start conducting and bringing the source voltage lower, which means that \$V_{GS}\$ will also be lower for the series transistors until the transistors closer to ground have conducted current.

It's also the case that the bodies of all the transistors are connected to ground, so if the source of a transistor is at a voltage above ground then there is effectively a negative voltage from the source to the body. The "body effect" causes the effective threshold voltage of the transistor to increase, making matters even worse.

Finally, even when all of the transistors in series are conducting you will have the series combination of their \$R_{DS}\$ values. Generally the transistors in series are made a little wider so that their series resistance is not so large.

Having said all of that, you will never achieve equal propagation delays for all input transitions. The reason is that when you have parallel transistors there will be some cases where all of those transistors are conducting simultaneously and other cases where only one of the parallel transistors is conducting, so the transition time of the output will vary greatly. Consider, for example, a 2-input NAND gate that has parallel NMOS transistors. Changing from a 00 input to a 11 input will cause two NMOS transistors to pull the output low quickly, but changing from a 00 input to a 01 input will cause a single NMOS transistor to pull the output low.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.