Full Adder driven by clock [FPGA/VHDL]

Question

I've got Ripple Carry adder (26bit) made from scratch.

entity Ripple_Carry26 is
port(
    A, B : in BIT_VECTOR(25 downto 0);
    Sum : out BIT_VECTOR(25 downto 0)
);
end entity;

Now I want to use it to update counter every time clock goes up. Counter is just simple register

entity Counter is
port(
    inp : in BIT_VECTOR(25 downto 0);
    clk : in BIT;
    qout : out BIT_VECTOR(25 downto 0)
);
end entity;
architecture Reg of Counter is
begin
    proc : process(clk)
    begin
        if clk'event and clk = '1' then
            qout <= inp;
        end if;     
    end process;
end architecture;

If I use port map to just connect stuff, it doesn't make sense, I only want to use the adder when clock goes up, but if I use process and say something like

if clk'event and clk='1' then

I'd like to say something like "now use the adder and add 1 to it" but I'm not sure how.

(I know I'm doing it too complicated, it's all learning purposes)

Every idea helps!

Answer 1

This is hardware design. If you want an adder, it must exist all the time, even if it is only being used some of the time. Therefore, you need to:

• instantiate the adder in your counter module
• connect the ports of the adder to signals
  • one input port gets the constant you want to add to the counter
  • one input port gets the current counter value
• in your clocked process, load the counter with the sum from the adder

The adder will be computing the next counter value all of the time, but that value will only get used when the clock edge occurs.