I need help with starting on the design of amplifier design project, given the following listed below specifications.

To be more precise, having learned about the different BJT amplifiers, such as the CE, CB, and CC amplifiers: How do I chose which one of the three and or in which order do I stage them, in order to accomplish the required specifications?

It is required to design a BJT amplifier that meets all of the listed below specifications.


The designed amplifier must be AC-coupled for the load and the signal source, but the coupling between its intermediate stages may be of AC or DC type, as per the designer’s choice. There are no restrictions in terms of using NPN or PNP transistors.

Note that there is no right or wrong design, as long as the aforementioned specifications are met.

The following below is a sample attempt at a possible solution.

possible solution, part 1

possible solution, part 2

Before starting to find a possible solution out of many possible combinations, and avoiding unnecessary calculations, I first started with an amplifier circuit with the amplifier block replaced by its equivalent-circuit model.

equivalent circuit model

I found and identified the next following listed below parameters:

parameter list

I am lost on how to continue this problem and find a possible solution. I need help with finding a possible circuit design that can be analyzed using DC analysis and AC analysis, with their corresponding equivalent circuit models.

Here is what I got close to. enter image description here

Now got a distortion. enter image description here

  • 1
    \$\begingroup\$ You've run afoul of the greater than 50k ohm input resistance spec. For your proposed first attempt, R1,R2 must be larger. \$\endgroup\$ – glen_geek Mar 31 '19 at 18:14
  • \$\begingroup\$ Finding a solution that satisfies the requirements is a different thing from analyzing that solution with non-linear DC and linearized small signal AC models. Do you expect all this to be done for you? Or is it enough to help start a design? \$\endgroup\$ – jonk Mar 31 '19 at 18:43
  • \$\begingroup\$ Welcome to EE SE! You are taking a very huge step here. Have you ever designed it in real life with simpler requirements than this? Does it work? Start learning it slowly little by little. The very first problem that I noticed is that, you don't even know where to start with. \$\endgroup\$ – Unknown123 Mar 31 '19 at 19:48
  • \$\begingroup\$ Any advice on approaching this question would be helpful. Including on learning examples on how to design BJT and MOSFET amplifiers, like the one illustrated above. Currently I am learning about this through the textbook called "Microelectronic Circuits, A.S. Sedra, K.C. Smith, 7th edition, Oxford University Press, 2014". Any useful sources would be much appreciated. For now help with starting on the design would be of much great help. \$\endgroup\$ – John Smith Mar 31 '19 at 20:12
  • \$\begingroup\$ Sounds like the prof is suggesting 50X gain in the first stage, and then buffering (emitter followers, voltage gain = 1) for the 2nd stage. For low distortion, you need to use NPN and PNP emitter followers; class "B" output stage. A challenging design task. \$\endgroup\$ – analogsystemsrf Mar 31 '19 at 21:49

Intro Note

Each of us hobbyists will have differing perspectives on how to approach your project and bring different strengths and weaknesses. The trained engineers here will have many fewer weaknesses, but still will have different strengths to apply. Since my betters haven't stepped in, I'll try and provide some thoughts at least about your specifications. Perhaps those thoughts will trigger your own ideas about how to approach your own solution ahead.

Conflicting Specs?

Some of the output specifications bother me.

They specify that when \$R_\text{L}=\infty\:\Omega\$ (in the unloaded case) that \$V_{\text{OUT}_\text{PP}}\ge 8\:\text{V}\$. Or, put another way, that \$V_{\text{OUT}_\text{PEAK}}\ge\pm 4\:\text{V}\$ when unloaded. They then specify that when \$R_\text{L}=1\:\text{k}\Omega\$ (the loaded case) that \$V_{\text{OUT}_\text{PP}}\ge 4\:\text{V}\$. Or, put another way, that \$V_{\text{OUT}_\text{PEAK}}\ge\pm 2\:\text{V}\$ when loaded.

The unloaded (\$R_\text{L}=\infty\:\Omega\$) voltage gain is supposed to be, \$A_\text{vo}=50\pm 5\$. So this would imply an input signal bracketed within a range of \$73\:\text{mV} \le V_{\text{IN}_\text{PEAK}}\le 89\:\text{mV}\$, prior to loading the output. Let's pick a number and select the obvious case where \$V_{\text{IN}_\text{PEAK}}= 80\:\text{mV}\$.

Now, they specify that the loaded (\$R_\text{L}=1\:\text{k}\Omega\$) case cannot cause a voltage gain less than 90% of the unloaded (\$R_\text{L}=\infty\:\Omega\$) gain. This suggests that, loaded, \$V_{\text{OUT}_\text{PEAK}}\ge\pm 3.6\:\text{V}\$.

But \$V_{\text{OUT}_\text{PEAK}}\ge\pm 3.6\:\text{V}\$ is not the same as \$V_{\text{OUT}_\text{PEAK}}\ge\pm 2\:\text{V}\$. So which is it? I suppose the only possible way to interpret the specifications is to go for the larger value based upon the 90% specification relating unloaded to loaded AC gain.

But this does leave me wondering if the person creating the specifications communicated their intent well. In my case, they certainly failed. Perhaps someone else can clear this up.

It's important because it makes a huge difference in output stage:

  1. If you are allowed to use the loaded \$V_{\text{OUT}_\text{PEAK}}\ge\pm 2\:\text{V}\$ specification, then you can just make sure that your collector resistor of the final (only?) CE stage is also \$1\:\text{k}\Omega\$. If the collector resistor matches the output load, then there's no need for an active sink/source driver (class-AB stage, for example) and you can get by, easier.
  2. If you are forced to use the 90% AC gain specification where the loaded \$V_{\text{OUT}_\text{PEAK}}\ge\pm 3.6\:\text{V}\$, then either you must use a CE stage with a collector resistor of perhaps \$110\:\Omega\$ (painful) or else you must use an active sink/source stage such as a class-AB output stage (also painful.)

Perhaps you can clear up this issue with the teacher?

Additional Thoughts

To reach a high input impedance of \$\ge 50\:\text{k}\Omega\$ with a CE stage almost requires either a bootstrapped CE stage (which you may not know how to design) or more than one CE stage (a pain) or else the use of a CE stage followed by a grounded emitter stage, together with global negative feedback to correct things and set the gain where you want it. (Grounded emitter designs have very high gain but it's also highly variable, temperature dependent, and... well, you need the global NFB to fix those problems.)

My own guess would be to use a bootstrapped CE stage to get the high input impedance and shoot for a voltage gain of perhaps 20, or so, knowing that there will be another stage. But the real problem is that I don't know what the output specifications really mean. They conflict, I believe, and it's important to resolve it before making further decisions. There is no possible way of getting a gain of 50, a high input impedance of \$50\:\text{k}\Omega\$ and a low output impedance of \$110\:\Omega\$ in a single bootstrapped stage. (At least, not with any management of the vagaries of realistic BJTs.)

You could plan a class-AB output stage. But then this might be gross over-kill if the specifications are cleared up in favor of a loaded \$V_{\text{OUT}_\text{PEAK}}\ge\pm 2\:\text{V}\$. Especially since you just might be able to do a bootstrapped design followed by a simple CE stage and get the job done much more easily.


Do you have to design a single stage for this? If so, there's something missing or wrong in the specifications. Are you familiar with bootrapped CE amplifier design? If not, you may need several stages to achieve the input loading specification. Do you feel you are supposed to use a class-AB output stage in your work? If not, then are they serious about the 90% specification?


Starting Notes

You've already mentioned you don't know about bootstrapped CE designs (really, the only way to go.) But I can see that you are familiar with the AC emitter resistor bypass method for getting larger AC gains without sacrificing the DC operating point.

You've mentioned distortion and the specifications also mention it. Clipping is, of course, one kind you really don't want to see. But there are other kinds related to a variety of factors. One of those factors is having the gain itself vary as the signal goes through one cycle (up, then down, and back up again.) This happens in part because of the AC emitter resistance known as little-\$r_e\$. There's also the Early Effect (basewidth modulation) that can add distortion. And there are a variety of other sources. There's no specific specification, though (other than forbidding clipping), so that means that so long as it "looks good enough" we can consider it okay. (It's all qualitative and not quantitative.)

You and I have agreed that we can hold to the loaded output swing specification. Let me be absolutely clear what this means to me. Unloaded, we must be able to support \$V_{\text{OUT}_\text{PP}}\ge 8\:\text{V}\$ without distortion. Loaded, we must be able to support \$V_{\text{OUT}_\text{PP}}\ge 4\:\text{V}\$ without distortion. Assuming the input signal isn't changed, this means the load can see an output signal that's \$\frac12\$ of the output signal we'd otherwise see, if unloaded by that load. This is the same thing as saying that the voltage gain is cut by \$\frac12\$ when you add the specified load of \$R_\text{L}=1\:\text{k}\Omega\$. (I'm going to completely ignore the "loaded voltage gain" specification of 90% until and unless I find a way to make it mean something that doesn't conflict.)

Those things said, I'd like to start with the final output stage since it now seems relatively easy to begin with it. The collector resistor is already determined. It's \$R_\text{C}=1\:\text{k}\Omega\$. (Assuming the AC coupling capacitor that also hooks up to the collector doesn't present a significant impedance at \$1\:\text{kHz}\$.)

Given that you have \$V_\text{CC}=15\:\text{V}\$, there's plenty of room for a higher quiescent emitter voltage and there's room to help avoid a portion of the Early Effect, too.

Trial: Single BJT, Single CE Output Stage Design

Here, I'm going to check out the idea of doing everything in a single CE stage.

  1. \$R_\text{C}=1\:\text{k}\Omega\$. This will meet the maximum loaded output voltage swing specification of \$V_{\text{OUT}_\text{PP}}\ge 4\:\text{V}\$, loaded by \$R_\text{L}=1\:\text{k}\Omega\$ (forming a voltage divider), when also meeting the maximum no-load output voltage swing specification of \$V_{\text{OUT}_\text{PP}}\ge 8\:\text{V}\$ with \$R_\text{L}=\infty\:\Omega\$.
  2. Given the unloaded \$V_{\text{OUT}_\text{PEAK}}=\pm 4\:\text{V}\$ and that \$R_\text{C}=1\:\text{k}\Omega\$, then \$I_{\text{OUT}_\text{PEAK}}=\pm 4\:\text{mA}\$. This isn't the quiescent DC collector current. It's the variation around that value.
  3. Given that \$A_{vo}=50\pm 5\$, the input source is \$V_{\text{IN}_\text{PEAK}}=\frac{V_{\text{OUT}_\text{PEAK}}=\pm 4\:\text{V}}{A_{vo}=50}=\pm 80\:\text{mV}\$, or \$\approx 57\:\text{mV}\$ RMS.
  4. Given \$r_e=\frac{V_\text{T}}{I_\text{C}}\$ (see Shockley equation) and that we can approximate \$A_{vo}=\frac{R_\text{C}}{R_{\text{E}_\text{AC}}+r_e}\$ the unitless sensitivity equation is \$\frac{\% A_{vo}}{\% I_\text{C}}=\frac{\frac{\text{d} A_{vo}}{A_{vo}}}{\frac{\text{d} I_\text{C}}{I_\text{C}}}=\frac{\text{d} A_{vo}}{\text{d} I_\text{C}}\cdot\frac{I_\text{C}}{A_{vo}}=\frac{R_\text{C}\cdot I_\text{C}\cdot V_\text{T}}{A_{vo}\cdot\left(V_\text{T}+R_{\text{E}_\text{AC}}\cdot I_\text{C}\right)}\$. We don't yet know the value of \$R_{\text{E}_\text{AC}}\$ or a few other parameters there. But we can, at least, perform quantitative testing of various ideas now.
  5. Let's assume we want to get full gain from this stage (we can't, but let's try) for a moment and that we can permit ourselves up to a 10% AC gain variation. Given (2) and (4) above, I find that we could just barely squeeze by with \$I_{\text{C}_\text{Q}}\approx 6\:\text{mA}\$ to meet \$A_{vo}=50\pm 5\$. The RMS collector current is then \$\sqrt{\left(6\:\text{mA}\right)^2+\frac12 \left(4\:\text{mA}\right)^2}\approx 6.63\:\text{mA}\$ RMS. If we can assume no worse that \$\beta=150\$ for the BJT, then this means the base current will be \$\frac{6.63\:\text{mA}}{150}\approx 44.2\:\mu\text{A}\$ RMS. The DC quiescent portion is \$\frac{6\:\text{mA}}{150}\approx 40\:\mu\text{A}\$, so the source will supply \$\sqrt{\left(44.2\:\mu\text{A}\right)^2- \left(40\:\mu\text{A}\right)^2}\approx 18.8\:\mu\text{A}\$ RMS. Ignoring all other loading (and there will be more), the best we can hope for then is an equivalent input resistance of \$\frac{57\:\text{mV}}{18.8\:\mu\text{A}}\approx 3\:\text{k}\Omega\$. And that's an idealist hope because it assumed the bias divider pair of resistors didn't add any further load to the input source.

No way will that meet the input specifications of \$50\:\text{k}\Omega\$.

So we've disproven that this can be done in a single CE stage with one BJT, whether a regular CE stage or a bootstrapped one. It's just not going to happen.

I'll do more, later, when I get a moment.

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  • \$\begingroup\$ It can be multiple stages with a limit of three stages. I am not familiar with bootstrapped CE amplifier design. Also unfamiliar with the Class AB Amplifier when analyzing it. For analyzing Class AB Amplifier would I have to analyze each transistor individually using Thevenin's Theorem for DC? \$\endgroup\$ – John Smith Apr 1 '19 at 20:46
  • \$\begingroup\$ @JohnSmith A class-AB amplifier has a gain of 1 (roughly) and uses at least two BJTs. So I think it is out of the picture (my opinion.) This leaves the question of the conflict I mentioned at the outset. The specs don't seem to be consistent. As I said, I would like to ignore the "90%" spec as being the one out of place. But without a discussion with your education staff, I can't tell if it is just my inability to understand them or if they are crazy and made a mistake in writing the specs. Do you have any idea? \$\endgroup\$ – jonk Apr 1 '19 at 20:50
  • \$\begingroup\$ The no smaller than 90% of the no-load voltage gain means that the A_v => 45. This implies that when load resistance is present the voltage output must be equal to or greater than 2 V (peak). If the input is 10 mV (peak), see Figure 1, than the output voltage is 4.5 V (peak). It seems obscure, indeed, but the set requirement is achieved. In my current design analysis I am ignoring it right now. Figuring out resistance values needed to be used than capacitor values. \$\endgroup\$ – John Smith Apr 1 '19 at 21:04
  • \$\begingroup\$ @JohnSmith A \$10\:\text{mV}\$ peak should produce a \$500\:\text{mV}\$ peak at the output with gain=50. (See unloaded gain specification.) But if you now kept that input peak but added \$R_\text{L}=1\:\text{k}\Omega\$ it would seem from the "loaded output voltage swing" spec that this could be only \$250\:\text{mV}\$ peak. That's a gain of 25, not 50. And it's not even close to a gain of 45. I admit I'm confused by the specs. The loaded output swing spec would seem to allow 1/2 the gain as when unloaded. Not true? \$\endgroup\$ – jonk Apr 1 '19 at 21:09
  • \$\begingroup\$ Having done the analysis on determining the resistance values in my simulations I have noticed that changing the capacitor values radically alter the voltage output. As a side question, is there a methodology on how to approach or learn how to approach such design problems instead of having to go through method of trial and error and analyzing possible combinations of different amplifiers? \$\endgroup\$ – John Smith Apr 1 '19 at 21:25

That looks like an impossible spec'.

Try this....


simulate this circuit – Schematic created using CircuitLab

Vs = +15V

Rin = 50k

Av(midband) = 50

f(-3dB) bandwidth = 16Hz to 50kHz

Isupply (for the op amp with no load) = 1.4mA

Minimum GBW of TL072CN is 2.5 MHz giving a natural upper -3dB frequency of 50kHz ( at a gain of 50).

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