FPGA too slow for my ripple carry adder?

Question

I wanted to make simple LED counter on my FPGA board (Cyclone IV EP4CE). I've made (from scratch - from NANDs) 4bit counter and 26 bit one. I have 26bit signal that is wired (port map) into 26 bit RIPPLE CARRY ADDER as one input and constant 1 as another input. I also have this with the 4 bit counter (wired to LEDs). Both are simple port maps (see code below).

Then I've got simple process that uses the precomputed value from 26 bit RIPPLE CARRY ADDER (current counter value + 1) and assigns it to counter. Then it check wheter counter has some value. If it does, it uses the precomputed LEDs value and assigns it to LEDs output in the same manner.

Code :

entity bit_register2led is
port(
    clk : in BIT;
    led : out BIT_VECTOR(3 downto 0)
);
end entity;

architecture leds of bit_register2led is
signal count : BIT_VECTOR(25 downto 0) := "00000000000000000000000000";
signal one : BIT_VECTOR(25 downto 0) := "00000000000000000000000001";
signal leds : BIT_VECTOR(3 downto 0) := "0000";

signal tmpC : BIT_VECTOR(25 downto 0) := "00000000000000000000000000";
signal tmpleds : BIT_VECTOR(3 downto 0) := "0000";
--. . .
begin
    adder1 : Ripple_Carry26 port map(A=>count, B=>one, Sum=>tmpC);
    adder2 : Ripple_Carry port map(A=>"0001", B=>leds, Sum=>tmpleds);
--  ‭0010111110101111000010000000‬ = 50 million - 50 MHz oscillator
    proc : process(clk)
    begin
        if clk'event and clk = '1' then
            count <= tmpC;
            if count = "10111110101111000010000000" then
                leds <= tmpleds;
            end if;
        end if;
    end process;
    led <= not leds;
end architecture;

This should add 1 to leds every second. It doesn't really work tho (it takes more than 1 sec). It's too slow and I'm getting warnings about timing requirements not met. Below are readings from Quartus timing analyzer, showing (I think at least..) my ripple carry adder is somehow too slow. I'm bit lost tho in all that. Not sure where the problem is.

Every help appreciated.

Answer 1

The delay in a ripple carry adder is dependent all the gates from the most significant bit down to the least significant bit. Odds are the adder you have implemented is to wide and the gate delays too great to meet timing constraints. This is why other implementations of adders were invented like the Carry Look Ahead adder.

Check the gate delay from the inputs to the carry bit, then multiply that by the number of adders. That number of bit's can't be greater than the clock (or I suppose you could wait another cycle).

So at this point, you could either:

1) Get a different implementation of the adder (like a CLA)
2) Slow down the clock
3) Make the adder smaller