I'm trying to simulate a simple common-emitter transistor amplifier presented as an example in Practical Electronics for Inventors in Qucs.

The circuity is identical to the one presented in the book. To investigate the behavior of the amplifier, I feed a 100 mV square wave at the input.

circuity from the book circuity

It shows the voltage on the DC-blocking capacitor - it gets charged and starts output a stabilized AC signal, but unfortunately, it failed to show any voltage from the output side.


I've attempted various output levels and frequencies of the square wave generator, from 1 volts to 20 volts, but none of the simulations showed the switching or amplifying behavior of the transistor.

I also tried to use an AC-signal source, but in this case, the simulation takes forever to complete. This particular issue has been discussed by the developers from the official project, who explained that Qucsator, the simulation engine, is more suitable for RF circuits simulation in frequency domain, and is known to have problematic behavior running simulation in the time-domain.

Following the suggestion of the developers, I tried to run the same simulation in Qucs-S, which instead uses NgSPICE as the simulation engine. Qucs-S generated the following netlist,

* Qucs 0.0.21 /home/gaizi/qucs/trans2.sch
.INCLUDE "/usr/local/share/qucs-s/xspice_cmlib/include/ngspice_mathfunc.inc"
* Qucs 0.0.21  /home/gaizi/qucs/trans2.sch
R2 0 _net0  1K
C3 _net1 in  0.32U 
R3 in 0  110K
R4 0 in  10K
R1 out 0  10K
V1 0 0 DC 20
R5 _net2 _net0  74
C4 0 _net2  16U 
QT_2N2222_1 out in _net0 QMOD_T_2N2222_1 AREA=1.0 TEMP=26.85
.MODEL QMOD_T_2N2222_1 npn (Is=1e-14 Nf=1 Nr=1 Ikf=0.3 Ikr=0 Vaf=100 Var=0 Ise=0 Ne=1.5 Isc=0 Nc=2 Bf=200 Br=3 Rbm=0 Irb=0 Rc=3 Re=1 Rb=10 Cje=2.5e-11 Vje=0.75 Mje=0.33 Cjc=8e-12 Vjc=0.75 Mjc=0.33 Xcjc=1 Cjs=0 Vjs=0.75 Mjs=0 Fc=0.5 Tf=4e-10 Xtf=3 Vtf=0 Itf=2 Tr=1e-07 Kf=0 Af=1 Ptf=0 Xtb=0 Xti=3 Eg=1.11 Tnom=26.85 )
V2 _net1 0 DC 0 SIN(0 1 1G 0 0 0) AC 1
echo "" > spice4qucs.cir.noise
echo "" > spice4qucs.cir.pz
tran 0.000990099 0.1 0 
write trans2_tran.txt v(in) v(out) 
destroy all


But in this case, the simulation doesn't even run.

$ ngspice netlist.cir 
** ngspice-30 : Circuit level simulation program
** The U. C. Berkeley CAD Group
** Copyright 1985-1994, Regents of the University of California.
** Please get your ngspice manual from http://ngspice.sourceforge.net/docs.html
** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html
** Creation Date: Sun Jan 20 13:41:46 UTC 2019

Circuit: * qucs 0.0.21 /home/gaizi/qucs/trans2.sch

Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

Fatal error: instance v1 is a shorted VSRC
doAnalyses: operation not supported

It says the voltage source v1 is shorted, which doesn't make sense.

My question is,

  1. The circuit doesn't output anything in the original Qucs simulation with a square wave signal source, why? Is there something wrong in my circuity, or that I've hit some known limitations of the simulation?

  2. Why can't the netlist generated from Qucs-S be simulated by NgSPICE? I've heard using multiple ideal voltage sources at the same time in a SPICE simulation may be problematic, then, what is the appropriate way to simulate the behavior of the circuit under a signal source?


V1 0 0 DC 20

The net connections for V1 are 0 and 0 i.e. you have both sides of the 20 volt battery connected to the same net. If you looked at your input waveform as it settles down you can see there is no bias voltage on the square wave and this also implies the supply voltage is connected incorrectly.

Compare this with R4: -

R4 0 in  10K

Clearly that is correctly connected between node 0 and node "in".

Aha, here's the problem: -

enter image description here

You have the 20 volt supply shorted out!

  • \$\begingroup\$ Eagle eyes! Thanks! ;-) Obviously this is exactly where the problem lies. I reconnected the battery and the simulation works like a charm now! I think this is one of the pitfalls of GUI tools in general, after watching a graphical representation for hours, one may no longer see a mistake like this one. \$\endgroup\$ – 比尔盖子 Apr 1 at 15:23
  • \$\begingroup\$ At least Falstad tells you there is an error if that happened \$\endgroup\$ – Sunnyskyguy EE75 Apr 1 at 15:57

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