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I've made a code in Verilog for a variable duty-cycle digitally controlled PWM generator. I will be using it in a system I am designing for controlling a buck-boost converter that will regulate the voltage of big solar panel.

My code works fine in simulations and here it's:

`timescale 1ns / 1ps
module PWM_gen(
    input clk,
    input [7:0] duty,
    output sig
    );

    reg [7:0] count = 8'b00000000;
    reg signal;
    wire [7:0] threshold;
    assign threshold = duty;



    always@(posedge clk)
    begin
    count <= count + 8'b00000001;
    assign signal = (threshold >= count);
    end
    assign sig = signal;
endmodule

The frequency of the PWM signal is

$$f = f_{clk}/2^N$$

where N is the size of the count register in bits. The duty cycle can be set by the duty input bus, if 50% duty cycle is required, duty must be set to 7F and so on.

The problem is, although it's working is it the correct implementation? I found a paper specifying different methods and designs of digital PWM generation circuits, the problem is should I follow those methods? what is usually used in the industry and what are the drawbacks of this implementation, I feel that it's very simple.

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  • \$\begingroup\$ This is not really an application where a programmable logic device makes sense - typically you would use an MCU timer. Your question is really too broad to be answerable, but 1) You should really register the duty cycle in the same clock domain so it does not change mid comparison (the actual issue is more complex) and 2) in some FPGA technologies you may need an explicit reset to initially start things off \$\endgroup\$ Apr 1, 2019 at 16:47
  • \$\begingroup\$ @ChrisStratton 1)you mean inside the always block? 2) Yeah I am aware of that, I still haven't put it into the board yet. As to why I am using aN FPGA, I don't know. I am aware that microcontrollers could be better suited to this application but I wanted to see if I could build most of the control system on a single chip. \$\endgroup\$
    – AdoobII
    Apr 1, 2019 at 17:04
  • \$\begingroup\$ An MCU is a single chip solution given the timer peripherals. "I don't know" is a plausible reason to experiment with an FPGA for learning but not a reason to deploy one where it is misfit. \$\endgroup\$ Apr 1, 2019 at 17:19
  • \$\begingroup\$ The question isn't really about the details of generating a PWM signal, it's actually about picking the correct duty cycle to generate. You haven't told us anything at all about how you're doing that, or how this PWM signal is actually used in the system. \$\endgroup\$
    – Dave Tweed
    Apr 1, 2019 at 17:19
  • \$\begingroup\$ @DaveTweed No that's not my question, sorry if I didn't word it correctly. I was asking about the correct implementation of the PMW generator and if I need to use a better approach. The correct duty cycle is irrelevant here since it will be changed to regulate the PV voltage. \$\endgroup\$
    – AdoobII
    Apr 1, 2019 at 17:22

1 Answer 1

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The only thing I would say about your PWM implementation is that it is way too wordy, with unnecessary signals. Here's a much more compact representation of exactly the same thing:

`timescale 1ns / 1ps
module PWM_gen (
    input       clk,
    input [7:0] duty,
    output      sig
);
    reg [7:0] count = 8'b00000000;

    always @(posedge clk) begin
      count <= count + 8'b00000001;
    end

    assign sig = (duty >= count);
endmodule
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  • \$\begingroup\$ The problem is I am always afraid of not using extra stuff because if an error occurs I will be lost and won't be able to fix it, I don't even know where to start with troubleshooting since Vivado doesn't always show why you were wrong with something. Thanks, I have learned a lot from the code above because I discovered that some stuff I knew was wrong. \$\endgroup\$
    – AdoobII
    Apr 1, 2019 at 17:50

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