If I want to invert a CML differential D-Flip Flop (Ex: hmc747lc3c) output before entering into a CML Counter(Ex: MC10EP016), is it as simple as flipping the signal lines before entering the counter? Or do I need to find an actual NOT gate? The reason I ask is because in LVDS logic flipping the signal lines acts as a NOT gate, but unlike LVDS CML is DC Biased.
Short answer: yes. I do this all the time with LVDS and MLVDS signals. Most times you can easily invert the logic in the device you've connected, so it is useful to do this to make routing easier and avoid layer transitions and the impedance mismatch that occurs when you do switch layers.
Yes, you are be able to simply reverse the inputs to invert the signal.
CML, like LVDS, uses symmetrical drivers for the P and N lines, which means there is electrically no difference between the lines.
In fact this is commonly done in PCIe which uses a CML variant. Routing can frequently be made easier by crossing the P and N lines of the data serial links. The protocol itself automatically corrects for the line inversion.
As a side note, contrary to you question, LVDS is also DC biased - typically to a common mode voltage of 1.2V.