# Arm Debug Interface vs CoreSight infrastructure in Cortex-M

Both documents define standards for communicating with DAP.

Slide 4 of this presentation says Debug features of Cortex-M4 are compliant with ARMv7 debug architecrute (CoreSight based) which to me implies that CoreSight is some lower level on which arm debug architecture is build.

But Arm official website makes it look like CoreSight is actually build on top of Arm Debug Interface v6. Because the spec for ADI is included as part of CoreSight overview.

Different page on Arm official website says that CoreSight is based on The debug and trace architectures which to me implies that CoreSight is build on top of ADI.

The CoreSight white paper appears to mention the same things as Arm Debug Interface: DAP, SWJ-DP, etc. Which makes me thing that it is the same specification as Arm Debug Interface, but maybe just renamed, or the draft version.

But Arm Debug Interface v6 seems to imply that these are possibly compatible but different technologies:

Compatibility between CoreSight and ARM debug interfaces:

ADIv6 is compatible with the ARM CoreSight architecture:

• ADIv6 can be used to access and control CoreSight-compatible components.

• The ADIv6 specification does not require debug components to comply with the CoreSight architecture.

After looking at the above sources I just feel more confused :)

Question: How do they relate to each other? Is one of them an expansion of the other?

• Questions here need to be specific and stand alone - ie, clicking on links cannot be a requirement to determine what you are trying to ask. What actual concrete conflicts have you found in those sources of information? What actual problem are you trying to solve? You certainly aren't licensing the core to put in your own silicon... – Chris Stratton Apr 2 at 17:33
• I added more details. I do not have an actual problem to solve, but I am starting development for cortex-M and trying to understand the different pieces that ARM provides and how they relate. – user10607 Apr 2 at 17:59
• If you only develop firmware then you don't really need to care about all of this, J-Link/Ozone/gdb/Eclipse/whatever takes care of this already. I think you would need to know the details at that level if you were making really performance-critical firmware, or your own debugger, or a new debug probe, or a new chip. The only practical "difference" I've encountered is that the firmware on a Cortex-M0 can't easily discover if a debugger is connected. – filo Apr 2 at 19:13
• From what I've seen, the CoreSight 20 pin header has 5 more active pins that are used for TRACE (clock + 4 bits). – Spehro Pefhany Apr 2 at 20:13