I stumbled upon an Schmitt-trigger oscillator circuit. I can fully understand the principles and its function, but what I cannot fully understand is the chain of inverters after it.

The circuit including the Schmitt-trigger oscillator and the inverter chain after it

In the above circuit I can understand the functionality of the first two inverters (for regenerative purposes/making the oscillation more "clear") but what is the purpose of the rest of the circuit, and especially of the 6th and the 7th inverter?


This is the original image (it is not that detailed, but I hope you can extract some more useful info)

enter image description here

  • \$\begingroup\$ I guess you cannot show the original \$\endgroup\$ Commented Apr 2, 2019 at 21:40
  • \$\begingroup\$ try this tinyurl.com/y2op5fnj \$\endgroup\$ Commented Apr 2, 2019 at 22:44
  • \$\begingroup\$ I can't see something, just a blank page. \$\endgroup\$
    – Arkoudinos
    Commented Apr 3, 2019 at 13:55

1 Answer 1


It somewhat depends on how the specific implementation technology deals with paralleled outputs, but my guess would be that this is supposed to generate a pair of nonoverlapping clock phases, commonly used in systems built using dynamic logic.

The idea is that only one of the outputs is high at a time, with no overlap during the transitions:

       ___________               _
______/           \_____________/
_____               ___________
     \_____________/           \__

Note how each output goes low before the other output goes high.

You can get the same effect (without the output conflicts) with a pair of cross-coupled NOR gates:


simulate this circuit – Schematic created using CircuitLab

If you switch to NAND gates, you get clocks that don't overlap in the low state.

  • \$\begingroup\$ I think I can kind of understand what you're saying, but it's not crystal clear to me. Could you please elaborate? For example, why is that important to generate this pair of non-overlapping transitions (and phases)? FYI this could be followed by a frequency divider (like a Johnson counter). \$\endgroup\$
    – Arkoudinos
    Commented Apr 2, 2019 at 21:20
  • 1
    \$\begingroup\$ This circuit works well to truncate the trailing edge of Phase 1 going low. from prop delay of INV but not the leading edge of Phase 1 nor the trailing edge of Phase2, so there is a still potential race \$\endgroup\$ Commented Apr 2, 2019 at 21:31
  • \$\begingroup\$ @SunnyskyguyEE75: No, there isn't. Run the simulation and see for yourself. \$\endgroup\$
    – Dave Tweed
    Commented Apr 2, 2019 at 23:10
  • \$\begingroup\$ I did, tinyurl.com/yxnl8nx6 you can see for yourself with slew rate limited inverters 0.5V/ns I meant overlapping edges on one and not the other. \$\endgroup\$ Commented Apr 2, 2019 at 23:31
  • \$\begingroup\$ This tinyurl.com/y47adhyt \$\endgroup\$ Commented Apr 2, 2019 at 23:53

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