I have four SPI-controlled chips which I want to control from Zynq-7020 via an FMC LPC connector. Each chip/device requires an SCLK, MISO, MOSI and CS line.
I'd like to give each device their own separate SPI bus, but for my given application, I don't have enough clock capable (CC) pins on the FMC LPC connector to give each device their own SPI SCLK. I do have enough pins to give each device separate MISO, MOSI and CS lines. There are a few options on what I could do, and I am wondering what the advantages/disadvantages of each would be:
1) Every device shares a single SPI bus (Separate CS lines, but shared SCLK, MISO, MOSI)
2) Shared SCLK, but separate MISO, MOSI, and CS lines for each device
3) Separate SPI buses, driving SCLKs through LA pins instead of CC pins on the FMC LPC interface. (I am not sure if my FPGA would like that I am driving a clock from a non-CC pin)
My target device is a PCB, what implications would each of the three options have on my design, and what would be the best option?