Trying to find out what is the possible maximum PWM frequency achievable with a low-cost FPGA with at least 2'000 "steps".

Being new in FPGA, I quite could not quite figure out how to extract this information from the datasheet.

Let's take ICE40LP384-SG32 as an example.

There are several pages concerning timings, but I am not sure what is relevant in this context and how the final max PWM frequency can be calculated.

Maximum sysIO Buffer Performance states a speed of 250 MHz.

With a clock frequency of 250 MHz, and a PWM counter of 2'000 steps that would yield a 125 kHz max PWM output frequency, is this correct or is there more timing consideration involved?

Could it be clocked faster than that? What is the relevant information there?

  • 1
    \$\begingroup\$ If you want higher switching speed with high pwm resolution all digital is not the way to go. An oscillator with voltage controlled duty cycle can be controlled with a DAC, e.g. a triangle oscillator followed by a comparator can be used. \$\endgroup\$
    – user110971
    Apr 3 '19 at 10:05
  • \$\begingroup\$ @user110971 Assuming of course that you have a very linear high-resolution DAC and a comparator with very small offset voltage... (In other words, DIGITAL! EVERYTHING MUST BE DIGITAL! :) ) \$\endgroup\$ Apr 3 '19 at 17:18
  • \$\begingroup\$ @ElliotAlderson offset voltage can be compensated for in the control loop. The requirements for the DAC are not too onerous. It’s only 2000 levels. \$\endgroup\$
    – user110971
    Apr 3 '19 at 17:29

If you just want to produce a PWM signal, most modern FPGAs have high-speed SERDES (serialize/deserialize) circuits built into their I/O that can run at tens of GHz. 10 GHz/2000 = 5 MHz PWM.

But often, PWM is just being used as a crude form of DAC. It's simple, but has severe bandwidth limitations. If that's what you're doing, other techniques such as delta-sigma modulation give you better tradeoffs.

  • \$\begingroup\$ Let me point out that a) FPGA with Serdes start at about 15 times the price of the model Damien mentioned and b) Serdes output drivers are not well suited to built a DAC - they are differential outputs and have quite strong signal shaping features that result in a high DNL/INL if used directly with a RCL filter. \$\endgroup\$
    – asdfex
    Apr 3 '19 at 13:29
  • \$\begingroup\$ @asdfex: Who said anything about driving a filter directly? Obviously, you'd need to convert the LVDS output to something more suitable first. That's what high-speed comparators are for. I'm just offering general suggestions, based on the limited information available from the OP. There was no mention of a cost constraint; that's just something you're reading into the question. \$\endgroup\$
    – Dave Tweed
    Apr 3 '19 at 13:33
  • \$\begingroup\$ Yes I'm talking about cheap fpga as I would need plenty of them. I will do some research on delta sigma modulation. \$\endgroup\$
    – Damien
    Apr 4 '19 at 5:57
  • \$\begingroup\$ 6.6 GHz SerDes can be found in Artix-7 FPGA, which are quiet cheap. \$\endgroup\$
    – Paebbels
    Apr 6 '19 at 23:32
  • \$\begingroup\$ Cheapest is 25$ at unit while the one linked is about 1$ @Paebbels \$\endgroup\$
    – Damien
    Apr 8 '19 at 6:05

Your are essentially correct. When generating PWM (or any periodic waveform) using counters, one limit for the maximum possible frequency will be equal to the input clock frequency divided by the maximum value of the counter.

In practice there may be other factors that limit the maximum frequency, such as the maximum frequency of an output pin. It is more likely that you would be limited by the ability of the logic to generate the PWM waveform. Your counter must have some kind of logic block that calculates count+1 as the next value in the counter. To control the duty factor you need another register that holds some value, and comparison logic to detect when the counter equals the register value (to toggle the output pin).

  • \$\begingroup\$ The internal logic can be pipelined to whatever extent necessary, so that rarely becomes the limiting factor. Back in the early days of slow FPGAs, I once pipelined a 22-bit DDS every 2 bits in order to get the speed that I needed. \$\endgroup\$
    – Dave Tweed
    Apr 3 '19 at 17:04
  • \$\begingroup\$ @DaveTweed But this is a counter we're talking about, so we need the latency to be 1 clock cycle. It seems to me that pipelining the +1 would mean that we count at half the clock frequency. True, the comparison logic could be pipelined if you account for the latency when setting the register values. \$\endgroup\$ Apr 3 '19 at 17:15
  • \$\begingroup\$ @ElliotAlderson LFSRs are what are used in such situations. It counts but not in an incremental sequence. The propagation delay is one gate. \$\endgroup\$
    – user110971
    Apr 3 '19 at 17:20
  • \$\begingroup\$ In addition, a counter could be done with flip-flop to increase speed? \$\endgroup\$
    – Damien
    Apr 4 '19 at 5:59
  • \$\begingroup\$ @Damien How else would you make a counter except with flip-flops? \$\endgroup\$ Apr 4 '19 at 18:42

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