Trying to find out what is the possible maximum PWM frequency achievable with a low-cost FPGA with at least 2'000 "steps".
Being new in FPGA, I quite could not quite figure out how to extract this information from the datasheet.
Let's take ICE40LP384-SG32 as an example.
There are several pages concerning timings, but I am not sure what is relevant in this context and how the final max PWM frequency can be calculated.
Maximum sysIO Buffer Performance states a speed of 250 MHz.
With a clock frequency of 250 MHz, and a PWM counter of 2'000 steps that would yield a 125 kHz max PWM output frequency, is this correct or is there more timing consideration involved?
Could it be clocked faster than that? What is the relevant information there?