i would like to add several (variable number N, fixed size) numbers in VHDL. In the image below you see how i want to do the additions. In this example there are N=6 numbers (A0 - A5). I have a component "adder" which takes as input two numbers and as the output the sum of the two numbers. In the image one adder is represented by two arrows combining two numbers.

Now my idea was to use a nested for...generate loop to instantiate the several adders and to connect them. But i don't know which range these loops should have or how to create the several "SumX"-signals to capture the results of the previous additions (because of variable N) and how to get the right indices in the for...genearate loops.

I'm looking forward to your suggestions!

Thank you!

enter image description here

  • \$\begingroup\$ Will it be easier for you if you assume N as a power of 2? \$\endgroup\$ – Eugene Sh. Apr 3 at 15:40
  • \$\begingroup\$ Why would you use a for loop to run this? What is your clock and clock requirements? Is this an academic exercise? \$\endgroup\$ – Voltage Spike Apr 3 at 15:44
  • \$\begingroup\$ @laptop2d It looks like a combinatorial circuit, if I understand correctly. The for loop is to generate such a circuit for an arbitrary N. \$\endgroup\$ – Eugene Sh. Apr 3 at 15:45
  • \$\begingroup\$ @EugeneSh. the thing that doesn't make sense is the sum2, and sum3, the above pattern doesn't look very repeatable for arbitrary N, and if it does need to be repeatable you'd need at least two examples to try and figure out what in the world the OP wants \$\endgroup\$ – Voltage Spike Apr 3 at 15:58
  • 2
    \$\begingroup\$ I suggest that you don't try to second-guess the compiler and just add the values up with one statement. Let the tools figure out the optimum way of performing the addition, based on your timing constraints. \$\endgroup\$ – Elliot Alderson Apr 3 at 16:05

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