i would like to add several (variable number N, fixed size) numbers in VHDL. In the image below you see how i want to do the additions. In this example there are N=6 numbers (A0 - A5). I have a component "adder" which takes as input two numbers and as the output the sum of the two numbers. In the image one adder is represented by two arrows combining two numbers.
Now my idea was to use a nested for...generate loop to instantiate the several adders and to connect them. But i don't know which range these loops should have or how to create the several "SumX"-signals to capture the results of the previous additions (because of variable N) and how to get the right indices in the for...genearate loops.
I'm looking forward to your suggestions!