Bandwidth of voltage divider with PMOS switch

Planning to measure (varying under switching e-bike load) voltage from a battery.

To step down the voltage panning to use a voltage divider and buffer the output to an ADC via an op-amp.

To completely switch off the device when the e-bike controller is off will need to switch off the current through the voltage divider (maybe this is an overkill considering how small the current is (~2mA), the controller's quiescent current is probably greater).

Planning to switch the divider with a PMOS.

How do I calculate the bandwidth of the divider + PMOS?

I suppose I should use Rds_on of the PMOS and Cin and Cout of the PMOS to get an equivalent circuit?

I first thought I would represent the PMOS as Rds_on in parallel with Cgs but I'm looking at PMOS datasheets and they only give Cin and Cout. simulate this circuit – Schematic created using CircuitLab

• Why not use $950k:50k//0.1uF$ and forget the switch – Sunnyskyguy EE75 Apr 4 at 23:22
• Would it be more susceptible to EMI with higher resistor values(lower current) and more error due to the op-amp's finite input impedance? – axk Apr 4 at 23:24
• The 0.1uF//50k=5ms so as long as wire loop area is minimized with twisted pairs or STP cable, spikes are attenuated so choose T=RC to exceed your ADC conversion time. – Sunnyskyguy EE75 Apr 4 at 23:27
• Check the $\mathrm{V_{GS}}$ rating of the PMOS -- most of 'em are only good to 20V. – TimWescott Apr 5 at 0:31
• @axk if you're not switching it too fast, you can just use a resistive divider. – TimWescott Apr 6 at 0:27 