0
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Circuit diagram of the circuit in question

Here is what I expected to happen:

A B C D
0 0 0 0
1 0 0 0
1 1 0 0
1 1 1 0
1 1 1 1
0 0 0 0
...

Initially, suppose all flip flops have output 0. Then, Q' of the last flip flop is 1, so all flip flops are in a stable configuration. On the next clock pulse, first flip one flips to 1 (because of Q' of last flip flop), and so on.

After the 3rd pulse of the clock, the flip flops are in the state 1 1 1 0.

On the next pulse, here's what I think should happen: Last flip flop takes in a 1, forcing it's Q' to become zero. That resets all the previous flip flops to 0. After resetting to 0, the output of first flip flop resets the last flip flop, effectively cycling back to the initial state with all flip flops being 0.

I reckon I have made some mistake in reasoning over here because it appears to not behave like that when I simulated it with QUCS. (I didn't have access to digital simulation in it but worked with transient simulation, so I might be wrong here too)

Any input is very much appreciated.

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closed as unclear what you're asking by Elliot Alderson, Voltage Spike, RoyC, Finbarr, Bimpelrekkie Apr 10 at 7:41

Please clarify your specific problem or add additional details to highlight exactly what you need. As it's currently written, it’s hard to tell exactly what you're asking. See the How to Ask page for help clarifying this question. If this question can be reworded to fit the rules in the help center, please edit the question.

  • \$\begingroup\$ Do the flip-flops have a synchronous reset or an asynchronous reset? \$\endgroup\$ – Elliot Alderson Apr 6 at 13:52
  • \$\begingroup\$ I'm very new to this but I'm using the DM74S74, if that helps \$\endgroup\$ – Arpit Saxena Apr 6 at 13:54
  • \$\begingroup\$ Then you should check the datasheet for the '74 and figure out whether the reset is synchronous or asynchronous, before you even begin trying to create a state table. \$\endgroup\$ – Elliot Alderson Apr 6 at 13:55
  • \$\begingroup\$ I'm sorry but I didn't know what synchronous and asynchronous meant. The set and reset on the '74 set / reset the output of the flip flop irrespective of the clock cycle and other inputs \$\endgroup\$ – Arpit Saxena Apr 6 at 13:57
  • \$\begingroup\$ You say what you expect to happen, but don’t tell us what is happening in the simulation. \$\endgroup\$ – HandyHowie Apr 6 at 14:29
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I understand your problem better now. It was only your PC implementation of QUCS and not this schematic and your understanding was perfect.

However, your explanation was unclear...

It would have been better to say...

Here is what I expected to happen:

(Shift-Right but skip 1111 with fixed rate Clk ↑)
Clk D  1 2 3 4
    1  0 0 0 0  initial state
 __________________
 ↑  1  1 0 0 0
 ↑  1  1 1 0 0
 ↑  1  1 1 1 0
 ↑  1  1 1 1 1  } 
    0  0 0 0 0  }  async pulse
    1  0 0 0 0  }  ( back to inital state )
 __________________
 ↑  1  1 0 0 0
    ... etc

1111 was skipped because is an unstable state
and latched off by R.

Your schematic used TTL with RS inputs being "Negative Logic = 0" used by TTL, which is not recommended for new design.

All discrete Flip Flops (FF) with RS Inputs are "Asynchronous Latches" with the CLK input for synchronous operation.

Now this Falstaad Simulation works
with any Browser using CMOS R=1

enter image description here

Trick for arrow symbol

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  • \$\begingroup\$ Thank you so much for putting in the time to deal with a beginner who didn't even know how to phrase his question. This exactly solves my problem. And thanks for suggesting a new circuit simulator that actually works. \$\endgroup\$ – Arpit Saxena Apr 10 at 3:29
  • \$\begingroup\$ Glad to help.... \$\endgroup\$ – Sunnyskyguy EE75 Apr 10 at 3:32
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Presumably at the point you expect 1111 you are seeing 0000.

If you look at the truth table in the data sheet for the 7474, you will see that the set and reset pins operate totally independently from the data and clock pins. As soon as the top bit goes high, the lower bits are reset to 0, which then resets the top bit.

Data sheet - http://www.ti.com/lit/ds/sdls119/sdls119.pdf

The data sheet says - “A LOW logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.”

This answer describes a synchronous reset - D flip-flop with a synchronous reset, R

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  • \$\begingroup\$ When the lower bits go 0, the upper bit should also be set to 0, right? I have the output of first bit connected to reset of the last \$\endgroup\$ – Arpit Saxena Apr 6 at 15:14
  • \$\begingroup\$ Yes, came back to correct this after thinking some more. \$\endgroup\$ – HandyHowie Apr 6 at 15:20
  • \$\begingroup\$ So, the 1111 state doesn't occur, right? (That's actually what I intended but I don't have access to a simulator and this being my first design with flip flops, I was unsure) \$\endgroup\$ – Arpit Saxena Apr 6 at 15:36
  • \$\begingroup\$ The 1111 state will occur very briefly. \$\endgroup\$ – HandyHowie Apr 6 at 18:00
  • \$\begingroup\$ Sync Reset D FF's do not exist in discrete IC's . That is simply an AND gated input for RESET = LO on next clk. that may be designed in a CPLD or FSM \$\endgroup\$ – Sunnyskyguy EE75 Apr 9 at 17:16
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All RS inputs are asynchronous. while CLR may not be!

This cct. causes a race after the clock edge on state 1110.

The clock shifts data right to 1111 for Q1234 followed by the start of rapid sequence of Q4! to reset Q1 which forces reset on Q234 which then removes the previous reset to Q1.

The state 1111 is truncated to 2 FF reset delays to state 0000 so the next Clocked output state is 0001. Thus 1111 is an asynchronous transient state and skipped.

One fix is to use a 5 input NAND to make a CLK gated Reset (I.e. synchronous edge) which then becomes an asynchronous race with a truncated pulse from Reset Delay time. It is also a potential race if there is a minimum pulse width.

My 1st statement should tell you how to solve this problem.

To avoid skipping 1111 you must use CLK to gate the condition to Reset, to make it synchronous!! and not just your async operation to shorten the reset pulse which clears the desired 1111 clocked state.

Such as this. ( there are other solutions as well )

enter image description here

Xilinx is the exception to this Rule with complex logic options but their descriptors are unambiguous.
enter image description here

Whereas primitive FF's of basic types JK,D,T and dual NAND or NOR gates used as "Registers" are alike AND all use asynchronous RS inputs.

Xilinx is different with a new set of primitives with a different names FDCE,FDPE,FDRE,FDSE which is not the same as primitive RS register.

This is a result of knowing the fundamental difference between a Latch and a Flip Flop. vs the specialized register which Xilinx clearly specifies with 4 different names and is not part of this question.

other

FWIW, (for what it's worth) TTL always used active low Asynchronous operations for RS and then when CMOS came out it was changed to mostly active high since the signals were symmetrical impedance for inputs but not all CMOS CLR's are active high..

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  • \$\begingroup\$ I think you mean that the RS inputs are asynchronous on the 74S74 flip-flops. This is not universally true for all flip-flops all of the time. \$\endgroup\$ – Elliot Alderson Apr 8 at 12:33
  • \$\begingroup\$ The next clocked output state would be 1000, right? \$\endgroup\$ – Arpit Saxena Apr 8 at 13:13
  • \$\begingroup\$ Is it possible that Q1 resets first, causing Q2 to reset, and even in the meantime Q3 and Q4 didn't reset? I get that it's a race condition but that much of delay should be enough to reset Q2 and Q3 \$\endgroup\$ – Arpit Saxena Apr 8 at 13:14
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    \$\begingroup\$ Elliiot The standard is self evident from experience of every basic FF with RS inputs ever made! Your CPLD example is not relevant to this. as they are given different names. FDRE/SE etc This is a clear distinction. ( pun intended) \$\endgroup\$ – Sunnyskyguy EE75 Apr 8 at 16:58
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    \$\begingroup\$ Oh my god. Now I see it. You are completely, truly, unquestionably correct and I was totally wrong! You win! I lose! \$\endgroup\$ – Elliot Alderson Apr 9 at 11:30

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