What's wrong with my interpretation of what should happen in the circuit and what's happening? [closed]

Question

Here is what I expected to happen:

A B C D
0 0 0 0
1 0 0 0
1 1 0 0
1 1 1 0
1 1 1 1
0 0 0 0
...

Initially, suppose all flip flops have output 0. Then, Q' of the last flip flop is 1, so all flip flops are in a stable configuration. On the next clock pulse, first flip one flips to 1 (because of Q' of last flip flop), and so on.

After the 3rd pulse of the clock, the flip flops are in the state 1 1 1 0.

On the next pulse, here's what I think should happen: Last flip flop takes in a 1, forcing it's Q' to become zero. That resets all the previous flip flops to 0. After resetting to 0, the output of first flip flop resets the last flip flop, effectively cycling back to the initial state with all flip flops being 0.

I reckon I have made some mistake in reasoning over here because it appears to not behave like that when I simulated it with QUCS. (I didn't have access to digital simulation in it but worked with transient simulation, so I might be wrong here too)

Any input is very much appreciated.

Answer 1

I understand your problem better now. It was only your PC implementation of QUCS and not this schematic and your understanding was perfect.

However, your explanation was unclear...

It would have been better to say...

Here is what I expected to happen:

(Shift-Right but skip 1111 with fixed rate Clk ↑)
Clk D  1 2 3 4
    1  0 0 0 0  initial state
 __________________
 ↑  1  1 0 0 0
 ↑  1  1 1 0 0
 ↑  1  1 1 1 0
 ↑  1  1 1 1 1  } 
    0  0 0 0 0  }  async pulse
    1  0 0 0 0  }  ( back to inital state )
 __________________
 ↑  1  1 0 0 0
    ... etc

1111 was skipped because is an unstable state
and latched off by R.

Your schematic used TTL with RS inputs being "Negative Logic = 0" used by TTL, which is not recommended for new design.

All discrete Flip Flops (FF) with RS Inputs are "Asynchronous Latches" with the CLK input for synchronous operation.

Now this Falstaad Simulation works
with any Browser using CMOS R=1

Trick for arrow symbol

Answer 2

Presumably at the point you expect 1111 you are seeing 0000.

If you look at the truth table in the data sheet for the 7474, you will see that the set and reset pins operate totally independently from the data and clock pins. As soon as the top bit goes high, the lower bits are reset to 0, which then resets the top bit.

Data sheet - http://www.ti.com/lit/ds/sdls119/sdls119.pdf

The data sheet says - “A LOW logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.”

This answer describes a synchronous reset - D flip-flop with a synchronous reset, R

Answer 3

All RS inputs are asynchronous. while CLR may not be!

This cct. causes a race after the clock edge on state 1110.

The clock shifts data right to 1111 for Q1234 followed by the start of rapid sequence of Q4! to reset Q1 which forces reset on Q234 which then removes the previous reset to Q1.

The state 1111 is truncated to 2 FF reset delays to state 0000 so the next Clocked output state is 0001. Thus 1111 is an asynchronous transient state and skipped.

One fix is to use a 5 input NAND to make a CLK gated Reset (I.e. synchronous edge) which then becomes an asynchronous race with a truncated pulse from Reset Delay time. It is also a potential race if there is a minimum pulse width.

My 1st statement should tell you how to solve this problem.

To avoid skipping 1111 you must use CLK to gate the condition to Reset, to make it synchronous!! and not just your async operation to shorten the reset pulse which clears the desired 1111 clocked state.

Such as this. ( there are other solutions as well )

Xilinx is the exception to this Rule with complex logic options but their descriptors are unambiguous.

Whereas primitive FF's of basic types JK,D,T and dual NAND or NOR gates used as "Registers" are alike AND all use asynchronous RS inputs.

Xilinx is different with a new set of primitives with a different names FDCE,FDPE,FDRE,FDSE which is not the same as primitive RS register.

This is a result of knowing the fundamental difference between a Latch and a Flip Flop. vs the specialized register which Xilinx clearly specifies with 4 different names and is not part of this question.

other

FWIW, (for what it's worth) TTL always used active low Asynchronous operations for RS and then when CMOS came out it was changed to mostly active high since the signals were symmetrical impedance for inputs but not all CMOS CLR's are active high..