I've designed an amplifier for a small ac signal (amplitude of around 5mV, frequency 252kHz) with a BJT (2N2222.)

The BJT is set up in a common emitter amplifier configuration, with the biasing resistors set up to provide a constant 0.7Vdc to the base.

I used blocking capacitors C2 and C4 to remove the dc bias by acting as a high pass filter.

However, even though I designed the circuit to have a voltage gain of 100, with cut off frequency of around 200kHz, I found my ac input signal was still being attenuated.

By changing the cut off frequency to 20Hz, I achieved a gain of close to 100. However, even by changing the cut off freq to 100kHz, my output signal is still attenuated.

Why is this?

enter image description here

  • \$\begingroup\$ What considerations have you given to the Miller effect? The 2N2222 BJT model in LTspice has, by default, CJC=8 pF (and CJE=25 pF.) Your gain is 100 and it looks like you are running about 9-10 mA for the quiescent collector current, at a guess. Since you designed this, perhaps you could discuss the details here, including how you treated the BJT parasitics in your analysis and set the values for your capacitors in the circuit. Finally, did you actually build this? Or are you discussing the attenuation that LTspice is showing you in simulation? \$\endgroup\$ – jonk Apr 6 '19 at 19:14
  • \$\begingroup\$ Hi, I didn't give any consideration to the miller effect, I wasn't aware of its existence (only in second year elec eng). You'd be correct for the gain and collector current. To design it, I followed this guide: hunter.cuny.edu/physics/courses/physics222/repository/files/pdf/… - I didn't take into account the parasitics, and designed it to have a collector current of 10mA and hfe of 150. I've been playing around with the capacitor values and at the moment have settled on a cut off freq of 100Hz, as this doesn't seem to attenuate my output. I haven't built this, \$\endgroup\$ – cookie99 Apr 6 '19 at 20:55
  • \$\begingroup\$ I'm discussing the attenuation LTspice shows in the simulation. Thanks. \$\endgroup\$ – cookie99 Apr 6 '19 at 20:57
  • \$\begingroup\$ When you get anywhere above perhaps \$100\:\text{kHz}\$ with standard small signal BJTs, you have to start worrying about stuff. Also, with high collector currents you run into other issues, as well. (Current crowding, ohmic parasitics...) A design should also take into account thermal effects and variations in parts (parts from a single BJT type might vary \$\pm 30\:\text{mV}\$ in their \$V_\text{BE}\$ (or more) and might vary over \$\beta\$, too. Given your desire for high gain which is pushing common BJT limits, you may find difficulty and instead want to split into two stages. \$\endgroup\$ – jonk Apr 6 '19 at 21:41
  • \$\begingroup\$ Is your signal really a \$50\:\Omega\$ source? Because, if so, common base is probably the way to go. If not, what is the source impedance? \$\endgroup\$ – jonk Apr 6 '19 at 22:13

Let's just say (for now) that your source impedance is \$R_\text{S}=9\:\Omega\$. (Or any other value you like, I suppose.) Your driving circuit appears to have very low output impedance. So a common base voltage amplifier design is indicated here, I think.

Let's design one.

Both the 2N2222A and the 2N3904 do fine with \$I_{\text{C}_\text{Q}}=10\:\text{mA}\$. So let's keep that choice you made for now. The basic layout for the common base design is the following:


simulate this circuit – Schematic created using CircuitLab

It looks a lot like a common-emitter design, and you can DC-bias it using a very similar approach, but the operation is different. The common-base design takes the capacitor normally used to accept a signal and apply it to the base of a common-emitter and grounds it (or ties it to \$V_\text{CC}\$.) With a large enough value for \$C_1\$, \$Q_1\$'s base is effectively tied to ground from an AC perspective. Now, the input signal is moved from the base to the emitter, via the usual DC-blocking capacitor, and the output signal is taken from the collector (as it would also have been with a common-emitter design.)

Summarizing, in changing from a common-emitter design to a common base design, the input signal is moved from the base to the emitter, the base is then AC-grounded, and the output signal is taken from the collector, same as before. You get a lot of potential voltage gain (which you apparently want) but you have to have a signal source capable of driving the emitter (which you apparently have.) And finally, your output signal is in-phase (instead of opposite-phase) and that helps to eliminate the Miller effect I'd mentioned elsewhere in comments, earlier. (The AC-grounded base, in effect, protects the collector signal from feeding back to the emitter input.) This improves the frequency response (which I think you want.) It's not uncommon to see RF amplifier stages using common-base (though they also use RF BJTs, too.)

Down to the design:

  1. \$A_{vo}\ge 100\$ and assuming \$V_{\text{IN}_\text{PEAK}}\approx 5\:\text{mV}\$ gives \$V_{\text{OUT}_\text{PEAK}}\ge 500\:\text{mV}\$. This output swings only over a full range of \$V_{\text{OUT}_\text{PP}}\ge 1\:\text{V}\$.
  2. In a common-base design, \$A_{vo}=\frac{R_\text{C}}{R_\text{S}+r_e}\$. Since \$R_\text{S}\approx 9\:\Omega\$ and since \$r_e\$ is set by your choice of quiescent current, this means \$R_\text{C}=100\cdot\left(9\:\Omega+\frac{V_T}{10\:\text{mA}}\right)\approx 1.2\:\text{k}\Omega\$ and it will quiescently drop \$12\:\text{V}\$ resulting in \$V_{\text{C}_\text{Q}}=8\:\text{V}\$.
  3. I like to see \$V_\text{CE}\ge 4\:\text{V}\$ at all times, so I'll set \$V_{\text{E}_\text{Q}}=3.5\:\text{V}\$. This means that \$R_\text{E}\approx \frac{3.5\:\text{V}}{10\:\text{mA}}=350\:\Omega\$. Call it the nearby standard value of \$R_\text{E}=390\:\Omega\$ and therefore \$V_{\text{E}_\text{Q}}=3.9\:\text{V}\$.
  4. The base resistor divider pair needs to supply the base current for \$Q_1\$ and it should maintain it's divider voltage reasonably well. You could nickel-and-dime exactly how much, but a rule that works pretty well is to use a divider current (don't confuse this with base current) of about \$\frac1{10}\$th the quiescent collector current. (Same as with common CE design thoughts for biasing.) This means about \$1\:\text{mA}\$ or so. The guaranteed minimum \$\beta\$ for both the 2N2222 and the 2N3904 when operating around \$10\:\text{mA}\$ is \$\beta=100\$. So \$R_2=\frac{3.9\:\text{V}+700\:\text{mV}}{1\:\text{mA}}=4.6\:\text{k}\Omega\$ and \$R_1=\frac{20\:\text{V}-3.9\:\text{V}-700\:\text{mV}}{1\:\text{mA}+100\:\mu\text{A}}=14\:\text{k}\Omega\$. Call them \$R_2=4.7\:\text{k}\Omega\$ and \$R_1=15\:\text{k}\Omega\$.


simulate this circuit

Try using that circuit in your simulation with your input source and see how it flies. You can increase \$R_\text{C}\$ a little to get more gain. But it will press the BJT more towards saturation, so be careful about just randomly changing one resistor to get more gain. (You might be able to press \$R_\text{C}=1.5\:\text{k}\Omega\$ in the above -- but that's squeezing into saturation and there's no more than that without re-calculating things. There's a process above and you can follow it if you really want more gain.)

If I made this, I'd use dead-bug construction. No solderless breadboard.

Keep in mind that there is a lot here that is NOT under managament. \$r_e\$ is significant, varies with temperature, and is close to the value of your assumed source impedance. I just threw in capacitor values with barely any thought at all, so feel free to adjust them. But it sounds as though you aren't looking for an exact gain. Just something in the ballpark of where you need it. You can always increase the gain by increasing \$R_\text{C}\$ but then you may need to reduce \$I_{\text{C}_\text{Q}}\$ so that the voltage drop across it is back within the right ballpark. Doing so will increase \$r_e\$ and therefore a temperature dependent bit of the voltage gain will be even more temperature dependent. But maybe that's fine.

| improve this answer | |

The input impedance is dominated by Beta * (reac + Re), paralleled by the base biasing.

Zin = 100 * (26 ohm/Ie_ma + 5)

Zin = 100 * (26 ohm / (5v/500 ohm) + 5 ohm)

Zin = 100 * (26/10mA + 5)

Zin = 100 * (2.6 + 5) = 100 * 7.6 = only 760 ohms.


Now for the gain. Gain is: Rcollector (all resistors/impedances on Collector, in parallel) divided by the series sum of all impedances in the emitter path including Z(C3) and "reac" and the 5 ohms. Know that reac is 1/gm, = 26 ohms/Iemitter_milliAmps.

At the Fcarrier, Z(C3) must be low compared to the 5 ohm resistor.

1uF at 1MHz is =j0.159 ohms.

1uF at 0.1MHz is -j1.59 ohms.

Make C3 be 1uF.


Make C2 and C4 also 1uF.

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  • \$\begingroup\$ I'm having trouble following your notation at the start, could you clarify further please? \$\endgroup\$ – cookie99 Apr 6 '19 at 20:59
  • \$\begingroup\$ The slope of the diode (the base-emitter diode) is 0.026/Idiode_amps. The 0.026 is kt/q in the diode, and we use this value in computing transconductance (GM); the inverse of GM is the dV/dI, or ohms, of the diode. That diode, plus your 5 ohms, scaled up by BETA, is the Rin of the transistor base. \$\endgroup\$ – analogsystemsrf Apr 7 '19 at 3:13
  • \$\begingroup\$ \$r_{Eac}\$ is the base emitter AC incremental resistance at stated bias current \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Apr 8 '19 at 6:32

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