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I've worked this problem before in Verilog and no problem at all. Tried the same problem with SV and the problems started. The idea is to just show numbers on the first 3 7-segments based on switches. At first, it just didn't work (the 7 segments were "off"). The code I used there was:

module top(SW, CA, CB, CC, CD, CE, CF, CG, AN);

input [3:0] SW;
output CA, CB, CC, CD, CE, CF, CG;
output [7:0] AN;

logic [6:0] seg = {CG, CF, CE, CD, CC, CB, CA};

assign AN = 8'b00011111;

bcd_decoder_0 dec1(.out(seg), .in(SW));

endmodule

You may ignore the instantiation to bcd_decoder_0, because it has proven to be right. As I said, the above code didn't work. Changing the data type of seg to "wire" solved everything:

module top(SW, CA, CB, CC, CD, CE, CF, CG, AN);

input [3:0] SW;
output CA, CB, CC, CD, CE, CF, CG;
output [7:0] AN;

wire [6:0] seg = {CG, CF, CE, CD, CC, CB, CA};

assign AN = 8'b00011111;

bcd_decoder_0 dec1(.out(seg), .in(SW));

endmodule

Why that happened?

Note: I'm using NEXYS4DDR board from Xilinx, CA...CG represent the segments and AN represents which 7-seg is selected.

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    \$\begingroup\$ In bcd_decoder_0, is out an output? (I hope so!). If so, you are trying to drive seg with multiple drivers (from dec1 and the declaration). This is not allowed for logic types, but is for wire types. \$\endgroup\$ – awjlogan Apr 6 at 22:02
  • \$\begingroup\$ It is! It's the output from the BCD decoder (7 bits representing each segment of the 7-segment). Could you explain what do you mean by "drivers"? \$\endgroup\$ – Miguel Duran Diaz Apr 6 at 22:05
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    \$\begingroup\$ By driver, I mean something trying to assign a value to a particular variable. When you have logic [6:0] seg = {...}, you are assigning ("driving") each bit in seg with Cx. Then dec1 is trying to assign (drive) a new value on to each bit in seg, so it is not clear what the value of seg should be, hence the error. \$\endgroup\$ – awjlogan Apr 6 at 22:09
  • \$\begingroup\$ While @dave_59 answered the actual question, this spiked my interest because it appears that this code relies on "reverse" driving through the net declaration assignment. I have never seen this done before, so I tried running a simulation of the code, which fails as expected. If it is true that this synthesizes and works in hardware, I am quite surprised. \$\endgroup\$ – pc3e May 5 at 11:29
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The difference is in the meaning of the RHS of the = in the signal declaration.

wire out = RHS;

is equivalent to

wire out;
assign out = RHS; // continuous assignment

And

logic out = RHS;

is roughly equivalent to

logic out;
initial out = RHS; // procedural assignment before time 0

This assignment happens before executing any other initial or always block.

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