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Accessing ram logic in Verilog with an initial block gives an error

"cannot synthesize initialized RAM logic <name> "

A part of the code will be as follows (I coded using Quartus Prime Lite 18.1):

module test(input [5:0] dm_abus,dm_wr_bus, output reg [5:0] 
dm_rd_bus,input rd_mem,wr_mem);

reg [5:0] data [0:63];

initial data[0] = 6'd10;
always @(dm_abus or rd_mem) if(rd_mem) dm_rd_bus = data[dm_abus];
always @(dm_abus or wr_mem or dm_wr_bus) if(wr_mem) data[dm_abus] = 
dm_wr_bus;

endmodule

In this code by removing the initial block or one of the two always blocks, then the code will compile successfully.

Reading and writing of the memory and giving initial values to the array should be essential though.

What can be done about this issue?

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  • \$\begingroup\$ What happens if you try to infer a synchronous RAM instead of an async RAM? \$\endgroup\$ – alex.forencich Apr 8 at 3:29
  • \$\begingroup\$ compilation as well as simulation with modelsim pssible with sync ram....wt went wrong with async ram then? \$\endgroup\$ – K.vindi Apr 8 at 3:47
  • 2
    \$\begingroup\$ Well, it's common for FPGA block RAM to only support synchronous operation. Async RAM may only be possible as distributed RAM, or perhaps only as latches. \$\endgroup\$ – alex.forencich Apr 8 at 3:55
  • \$\begingroup\$ What device are you targeting? \$\endgroup\$ – DonFusili Apr 8 at 8:20
  • \$\begingroup\$ Didn't get it.what did you mean? \$\endgroup\$ – K.vindi Apr 9 at 11:08

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