1
\$\begingroup\$

I got some 0.1uF ceramic capacitor in front of my mcu IO pins to smooth the inputs values/spikes pcb

I was wondering if this placement is bad or not because their position is "over" the input so maybe (unexpected?) current will "hit" the pin before being smoothed by capacitors.

Is it something like this worth the layout refactor effort? enter image description here

Notes:

  • input pins will detect LOW values
  • input pins are pulled up by R6,R8,R10 resistors
  • ground wires are still visible because I didn't ratsnest'ed yet :)

Edit: this is the schematic for each input

enter image description here

Improve this question
\$\endgroup\$
  • 3
    \$\begingroup\$ I have doubts if the capacitors (can) do anything, if the inputs are pulled low by an open collector/drain output then the caps only filter when the inputs turn HIGH. You show no schematic so I can only assume. These caps aren't for decoupling so their placement isn't critical. \$\endgroup\$ – Bimpelrekkie Apr 8 '19 at 12:42
  • \$\begingroup\$ @Bimpelrekkie thank you for your comment, I added an input schematic! I'm more worried about filtering (small) spikes like described here digikey.com/en/articles/techzone/2012/apr/… \$\endgroup\$ – Rubens Apr 8 '19 at 13:04
  • \$\begingroup\$ That article deals with resonances and spikes due to long wires. Do you have long wires? If not your main issue is contact bounce. To counter that I would not use 100 ohm (R5) and 0.1uF (C1), you get a very short timing constant that way. Instead I'd use: R1 = 1 k, then R6 needs to be higher, I'd use 10 k ohm. \$\endgroup\$ – Bimpelrekkie Apr 8 '19 at 13:12
  • \$\begingroup\$ I understand the higher resistor to decrease input "sensitivity". Since installation will be "out of my jurisdiction" I was assuming to get at least minimal layout design to avoid these classic issues, especially long wires noises and small spikes without getting mad trying to buffer large transient with some more complex layout design \$\endgroup\$ – Rubens Apr 8 '19 at 15:12
0
\$\begingroup\$

I was wondering if this placement is bad or not because their position is "over" the input so maybe (unexpected?) current will "hit" the pin before being smoothed by capacitors.

For any frequency signal that an MCU input can respond to, the position of the capacitor "before" or "after" the pin does not matter. Only that it's within a few cm of the pin.

I would not change the design you have.

On the other hand, I'd avoid double-sided through hole design. Where you have your resistors located, you won't be able to inspect their solder joints after the MCU is installed. I'd move them out from under the MCU also.

Improve this answer
\$\endgroup\$
  • \$\begingroup\$ Ok thank you for this clarification! This is going to be a single sided through hole design and the MCU will stand on classic female headers so I can take it away if needed. You are right, is not the best solution to check a "powered running system" but can save a bit of space :) I'll try to figure out if I can do something about this! \$\endgroup\$ – Rubens Apr 8 '19 at 18:00
0
\$\begingroup\$

The way that you tell is by calculating the parasitic resistance and inductance of the traces. Then draw the parasitic resistance and inductance of the traces in the schematic.

For example: A 12 mil trace that is 1" long has ~8nH of inductance 35mΩ of resistance. So if you had a 1" 12mil trace between ground and a capacitor, this is how much inductance and resistance the trace would add to the circuit. If the parasitics start making a difference, then consider changing the length, width or routing of the circuit. Typically parasitics don't matter unless the circuit is high frequency (10MHz+) or high current.

Improve this answer
\$\endgroup\$
  • \$\begingroup\$ Thank you, it's absolutely interesting! This pcb will be small (10x6cm) with through hole components and traces will be sized to be printed/routed at home. There is an electromagnetic relay at the other end of this board with at most 2A 230AC (with varistors, tvs and rc filters to limit issues). At the moment have 10 v1 prototypes in action since a couple of year and this is going to be v2, with a different set of components/software. The main hw failure for 1 of them was one of these input, others didn't get same issue. \$\endgroup\$ – Rubens Apr 8 '19 at 18:28
  • \$\begingroup\$ meta.stackexchange.com/questions/126180/… \$\endgroup\$ – Voltage Spike♦ Apr 8 '19 at 18:34

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.